用verilog-ams语言写EEPROM浮栅管和控制管的模型

也可以用什么软件交换

`include "disciplines.vams"
`include "constants.vams"
module eeprom_block(wl, prog, bit_11_to_0, vs);

inoutwl, prog, vs;
inout[11:0] bit_11_to_0;
genvari, j;

electrical wl, prog, bit_11_to_0, vs, gnd;
electrical [11:0] fg;
parameter integer mem_11 = 1 from [0:1];
parameter integer mem_10 = 1 from [0:1];
parameter integer mem_9= 1 from [0:1];
parameter integer mem_8= 1 from [0:1];
parameter integer mem_7= 1 from [0:1];
parameter integer mem_6= 1 from [0:1];
parameter integer mem_5= 1 from [0:1];
parameter integer mem_4= 1 from [0:1];
parameter integer mem_3= 1 from [0:1];
parameter integer mem_2= 1 from [0:1];
parameter integer mem_1= 1 from [0:1];
parameter integer mem_0= 1 from [0:1];
parameter real v_15 = 15;
parameter real v_16 = 16;
parameter real v_5= 5;
parameter real v_3= 3;
parameter real v_1= 1;
groundgnd;
analog
begin
@(initial_step)
begin
V(fg[0])<+ mem_0;
V(fg[1])<+ mem_1;
V(fg[2])<+ mem_2;
V(fg[3])<+ mem_3;
V(fg[4])<+ mem_4;
V(fg[5])<+ mem_5;
V(fg[6])<+ mem_6;
V(fg[7])<+ mem_7;
V(fg[8])<+ mem_8;
V(fg[9])<+ mem_9;
V(fg[10])<+ mem_10;
V(fg[11])<+ mem_11;
end
@(cross((V(wl)-v_16), +1)) begin
if(V(wl) >= v_16 && V(prog) >= v_16 && V(vs) <= v_1)
begin
V(fg[0]) <+ 1;
V(fg[1]) <+ 1;
V(fg[2]) <+ 1;
V(fg[3]) <+ 1;
V(fg[4]) <+ 1;
V(fg[5]) <+ 1;
V(fg[6]) <+ 1;
V(fg[7]) <+ 1;
V(fg[8]) <+ 1;
V(fg[9]) <+ 1;
V(fg[10]) <+ 1;
V(fg[11]) <+ 1;
end
else if(V(wl) >= v_16 && V(prog) <= v_1)
begin
for(i=11;i>=0;i=i-1)
begin
if(V(bit_11_to_0[i]) >= v_15)
begin
V(fg[i]) <+ 0;
end
end
end
end
if((V(wl)>= v_3) && (V(wl) <= v_5))
begin
for(j=11;j>=0;j=j-1)
begin
if(V(fg[i])==0)
begin
V((bit_11_to_0[i]),vs) <+ 0.3;
end
else
begin
V((bit_11_to_0[i]),vs) <+ 2.8;
end
end
end
else
begin
V((bit_11_to_0[11]),vs) <+ 2.8;
V((bit_11_to_0[10]),vs) <+ 2.8;
V((bit_11_to_0[9]),vs) <+ 2.8;
V((bit_11_to_0[8]),vs) <+ 2.8;
V((bit_11_to_0[7]),vs) <+ 2.8;
V((bit_11_to_0[6]),vs) <+ 2.8;
V((bit_11_to_0[5]),vs) <+ 2.8;
V((bit_11_to_0[4]),vs) <+ 2.8;
V((bit_11_to_0[3]),vs) <+ 2.8;
V((bit_11_to_0[2]),vs) <+ 2.8;
V((bit_11_to_0[1]),vs) <+ 2.8;
V((bit_11_to_0[0]),vs) <+ 2.8;
end
end
endmodule

自己先写的如何修改?