微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 微波和射频技术 > RFIC设计学习交流 > PLL内的电容电阻对BW的影响

PLL内的电容电阻对BW的影响

时间:10-02 整理:3721RD 点击:
对于二阶PLL(滤波器一个电阻,一个电容串联)会产生两种状态。一个是过阻尼,一个是欠阻尼。那么这两个状态下,电阻和电容的值对于PLL的带宽分别有什么影响呢?

自己顶一下,求大家帮助。

analog PLL loop BW = 1/(RC)

为何没有临界阻尼呢?

dampping frequency is transition, PLL lock time constent about 8~10 time constant in loop time domain equation exp(-1/T)*dampping term,T: time constant

Sorry, wrong typing
dampping frequency is transition, PLL lock time constent about 8~10 time constant in loop time domain equation exp(-t/T)*dampping term,T: time constant

BW=1/RC? 跟Icp, Kvco 没有关系么?

临界阻尼的状况呢?

phase margin

如果只是在做一个简单的RC滤波器的话,BW=1/RC是对的。




Assume a linear system Y=H*X, H = 1st ~ nthorder
Derive H=Y/X in Laplace s-domain
Then transfer H back to the time domain
You can get several term with different time constant.
Since smaller time constant will decay faster (you can see these term to be the system transition).
You can approximate the system time constant to be the maximum time constant.

In this analog PLL case, X = input clock, Y = output clock, H = PLL system

H of PLL system is NOT the same as LPF RC, VCO is another order of low pass on top of RC filter itself...and Kcp and Kvco are also very important on loop gain which affect the PLL BW for sure...-->The conclusion is PLL BW is NOT a simple RC low pass filter, a lot more are involved actually for the PLL BW, thus the conclusion on the relationship between the filter RC and PLL BW could be correct ONLY when the loop filter is plugged in a more specific PLL system. In other words, the relationship could be different on different PLL system providing that you need to make the PLL stable first, otherwise the BW means nothing at all.
如果可能还是用中文交流比较好。这样对论坛兄弟们可能会方便些。

開迴路 BW 就是跟 lock time 有關 怎麼會不重要?
PLL 系統是負回授系統 Kvco等參數當然必須在迴路函數中 我說的H是用輸入跟與輸出看 相位微分就是角速度鎖相就會鎖頻 你推導一下數學就會了解 這完全與OP負回授是同一件事 H 的setting time 就是 PLL 的setting time 這是數學問題 PLL當然不會是一階系統 但是自外面看就跟濾波器一樣(當然不是一階這麼簡單) 麻煩推導一下數學

由輸入與輸出看 w_in(t) w_out(t) 類比式 PLL就是一個 有gain (M/N or fractional-N) 的 filter

如果没搞清H是什么的情况下数学是帮不了忙的。只有把H完整带进去再去导数学而且限制条件是系统phase Margin一定做为先决条件,可能这时导出的关系才可能有意义。否则可能越导数学距实际可用的PLL越远,要它何用?恐怕只能是为导数学而导数学了,因为它只是一座漂亮的“空中楼阁”,并没有实际实用价值。
BTW, it seems better to discuss in English if you like...

H在以下連結有答案
http://wenku.baidu.com/view/dd833dd284254b35eefd3495.html
做類比電路數學有大用 千萬不能輕視數學

数学大有用----完全同意。
数学在工程中是有力工具不假,甚至不可或缺,但运用是否得当却直接决定了数学是否可以发挥其应有的作用,如果运用不当甚至会受到误导。目标设定明确,工具运用得当,在解决工程问题中缺一不可。

看来这位兄弟来自台湾

麻烦您还是用英文把,你的繁体字看的头晕

Ok, no problem!

这你还是要看PLL的设计中,有这方面的专门设计的

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top