求助个问题

• The circuit above shows an inverter self biased using a resistor Rbias. An ac signal vs is coupled to the input and the output is incrementally shorted for ac signals. What is iout? What will you do to make iout/vs approximately equal to the gm of the inverter and independent of Rbias?
  

目测坛子里能解决这个问题的不超过1%

我有点怀疑这算不算是个问题，'大侠'阁下

大神，你告诉我这个为何不算是问题?

我认为gm*Rbias>>1就可以了，坐等高手分析

希望大神帮忙解答

对于你这个不算是问题啊，应该是这个过程把：iout=Vs/Rbias+Vsgm得：iout/Vs=gm+1/Rbias.若gm>>1/Rbias.则iout/Vs=gm,与Rbias无关。

我赞同你的观点

这是在求助?似乎在立擂么

呵呵，提出这个问题后没人解答才这么说的，激将法呵呵，用的有点搓。现在发现这个是不算个‘问题’啊

我觉得还应该考虑输入信号vs的频率，频率不同couple到gate的电压信号也不同，包括幅值和相位；R既有前馈也有反馈，觉得不是这么简单的。

Clager,就暗示排除你说的情况了

输入信号vs和 隔直电容Clarge 及隔直电容Clarge 后的信号间的关系是怎样的?包括幅值和相位。我信号系统知识几乎为零。呵呵

比如vs频率相当低，那是couple不到gate上的，因为这是一个高通；如果vs频率非常高，couple电容后面就等效为电阻R和反相器输入电容并联，这样反相器gate端还是要考虑电阻R的分压。

charge sensitive amplifier used for charge pulse amplification and reshaping

你把问题复杂化了

1.
I think the input capacitor is a large external DC blocking capacitor. So you want to do a circuit with DC block function (high pass filter) &a low pass function (low pass the high frequency noise). So this circuit has to play the role of a band pass function. So I guess your signal has it`s different DC level & you want it`sAC component. If this is true, the large external DC blocking cap. has very small impedance (for AC input signal) so the inv`s feed back loop can not overcome the external AC signal through the cap.,so your inv`s input must jump with the input signal.
2. Let`s think about when you ground the input signal. What is the stable state of the inv.?
Since VDD = 6V > Vtn+|Vtp|, the inv`s stable state will be two diode connect PMOS & NMOS between VDD & GND. So we can know that use the inv to play a OP`s function is not wise, because its current is very sensitive to power level. So I suggest you can modify your circuit ( inv. ) use a PMOS current source & a NMOS (change inv`s PMOS as a current source). This can be the same function & bias current is fixed.
3.For 1. problem, external signal feed through the external large cap. make the inv`s input jump with the input signal. I suggest you can put a resistor between external large cap. & inv`s input (inside chip). Then your circuit will become input R1 (connect to PAD, connect to the external cap.), feed back R2, (R1,R2 ratio can modify the external signal swing & internal output swing).Inv`s PMOS change to a PMOS current source, so it`s current will fixed. The DC bias point of the NMOS will like PMOS current feed to the diode connected NMOS. With this configuration the NMOS`s input point will not jump with input signal, solve the loop stability issue is your work. Use large enough R1 & R2, that the PMOS & NMOS can control the loop when AC input signal is comming.
4. R1 can also be a ESD protection resistor.
5. Suggust you can use a unit gain buffer to do the same thing (use a large R, pull the buffer`s input to VDD/2).
6. Suggust you can use very week pull-up or pull-down resistor (large R), or pull to your predefine voltage then connect a level shifter, can also do the same thing.

LZ一直就这样，这两天看她的问题和讨论实在费劲的很

mark。