CMOS Ids随温度的变化升高还是降低？

Good question.
Usually, for 90nm above technology, Ids is decreased with temperature increasing. That is to say, mobility is dominate.
However, from 90nm to 65nm/45nm, there is reverse trend for Ids at lower operation voltage. ids is increased with temp increasing. That is an challenge for the PVT condition selections.

楼上应该不错，我只知道tsmc .13和.11工艺随着温度的升高Ids下降

这个问题要考虑在一定的Vgs条件下, Ids与(Vgs-Vth)的平方成正比, 故随T变化时, 在Vgs大于或小于Vth时, Ids自然也有不同的趋势.

好奇地问一句, 你是不是刚面试回来, 沪上有家公司老总很爱问这个问题.

it depends on you bias circuit.
u may design an ptat current or ntat current

完全同意！

vth 和 beta 都是负温度系数，可是beta占主导，ids下降，0.8工艺。hspice很容易方得到的