使用hspice进行开环仿真的问题
时间:10-02
整理:3721RD
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今天看到罗广孝老师的cmos模拟电路设计与仿真其中的对一个折叠共源共栅结构的开环仿真不太理解网表如下
EX 11.1 CASCODE OP AMPS
.option post=2 numdgt=7 tnom=27
*VIN+10DC0pwl(0 -1 10n -1 20n 1 1u 1 1.01u -1 2u -1 2.01u -.1 3u -.1
3.01u .1
*+4u .1 4.01u -.1 5u -.1)
VIN+10DC0 ac 1
VNI-20dc 0ac 0
VDD30DC2.5
VSS04DC2.5
CL5010PF
X1 1 2 3 4 5 OPAMP
.SUBCKT OPAMP 1 2 3 4 5
m18164NMOSl l=1uw=35.9u
m29264NMOSl l=1uw=35.9u
m36744NMOSl l=1uw=91.6u
m4811 33PMOSl l=1uw=80u
m5911 33PMOSl l=1uw=80u
136
m613 12 88PMOSl l=1uw=80u
m7512 99PMOSl l=1uw=80u
m814 13 15 4NMOSl l=1uw=36.36u
m9513 16 4NMOSl l=1uw=36.36u
m10 15 14 44NMOSl l=1uw=36.36u
m11 16 14 44NMOSl l=1uw=36.36u
m12 12 744NMOSl l=1uw=114.53u
m13 11 12 10 10PMOSl l=1uw=80u
m14 10 11 33PMOSl l=1uw=80u
R111 122K
R213 142K
VBIAS 70-1.6
.MODEL NMOSl NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOSl PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=0.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P
+LD=0.014U TOX=14N
.ENDS
.op
*.tf v(3) vi1
.dc VIN+-0.005 0.005 100u
.print dc v(5)
.ac dec 10 1 10MEG
.print ac vdb(5) vp(5)
*.dc VIN+-2.5 2.5 0.1
*.iplot v(5)
*.tran 0.05u 5u 0 10n
*.print v(5) v(1)
.end
主要是vin+和Vin-的初始dc 都是设置为0我觉得这样相当于m1m2的直流偏置为0就不导通了啊可是仿真结果是正常的不理解啊
我换了个电路把输入也一样设置结果两个管子果断cutoff了
另外 对开环和闭环仿真的概念不很清楚一开始我以为区别就是子电路有没有补偿电容最后发现所用的子电路是相同的
新手见笑了
EX 11.1 CASCODE OP AMPS
.option post=2 numdgt=7 tnom=27
*VIN+10DC0pwl(0 -1 10n -1 20n 1 1u 1 1.01u -1 2u -1 2.01u -.1 3u -.1
3.01u .1
*+4u .1 4.01u -.1 5u -.1)
VIN+10DC0 ac 1
VNI-20dc 0ac 0
VDD30DC2.5
VSS04DC2.5
CL5010PF
X1 1 2 3 4 5 OPAMP
.SUBCKT OPAMP 1 2 3 4 5
m18164NMOSl l=1uw=35.9u
m29264NMOSl l=1uw=35.9u
m36744NMOSl l=1uw=91.6u
m4811 33PMOSl l=1uw=80u
m5911 33PMOSl l=1uw=80u
136
m613 12 88PMOSl l=1uw=80u
m7512 99PMOSl l=1uw=80u
m814 13 15 4NMOSl l=1uw=36.36u
m9513 16 4NMOSl l=1uw=36.36u
m10 15 14 44NMOSl l=1uw=36.36u
m11 16 14 44NMOSl l=1uw=36.36u
m12 12 744NMOSl l=1uw=114.53u
m13 11 12 10 10PMOSl l=1uw=80u
m14 10 11 33PMOSl l=1uw=80u
R111 122K
R213 142K
VBIAS 70-1.6
.MODEL NMOSl NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOSl PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=0.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P
+LD=0.014U TOX=14N
.ENDS
.op
*.tf v(3) vi1
.dc VIN+-0.005 0.005 100u
.print dc v(5)
.ac dec 10 1 10MEG
.print ac vdb(5) vp(5)
*.dc VIN+-2.5 2.5 0.1
*.iplot v(5)
*.tran 0.05u 5u 0 10n
*.print v(5) v(1)
.end
主要是vin+和Vin-的初始dc 都是设置为0我觉得这样相当于m1m2的直流偏置为0就不导通了啊可是仿真结果是正常的不理解啊
我换了个电路把输入也一样设置结果两个管子果断cutoff了
另外 对开环和闭环仿真的概念不很清楚一开始我以为区别就是子电路有没有补偿电容最后发现所用的子电路是相同的
新手见笑了
因为VSS04DC2.5