Some problem with TSMC18rf inductor device

Our designing environment is caliber v2006.1_25.26 embedded into Cadence IC5.10.41.169. And the PDK is “tsmc181p4mmmrfpdk_v13”.Now we are suffering from some problems with TSMC18RF PDK and the Calibre LVS.

The schematics and the layout can be created correctly, and the pre-simulations can also be taken. The layout can pass the Calibre DRC check smoothly. But it seems that the Calibre LVS doesn't work.

The first problem is about the NMOS_RF and PMOS_RF device identifications. the RFMOS with DNW and guard ring is used in our design, and the dummy poly on each side of the RFMOS layout is created automatically or manually. The RFMOS can be identified by Calibre LVS correctly on this condition. But the dummy poly and the active region should not be floated. When we connect the dummy poly to the right voltage level(PMOS_RF to VDD, NMOS_RF to GND), the problem emerges. Calibre LVS stops with errors tell that "Corresponding cells could not be
identified. Nothing in layout.". And the Extraction Report tells that "

<<
WARNING: BAD DEVICE on layer nrgate_4t_nthin at location (-98.41,50.81) in cell Example

(Too many pins).

Found 6 interaction(s):

Pin on layer d_tndiff, net 5 at location (-95.63,52.31)

Pin on layer poly, net 3 at location (-97.68,52.31)

Pin on layer s_tndiff, net 3 at location (-98.41,52.31)

Pin on layer psub, net 1 at location (-98.41,52.31)

Auxiliary shape on layer nrgate_rf4t at location (-97.68,52.31)

Pin on layer s_tndiff, net 4 at location (-96.78,52.31) (extra pin)

Possible Element Names: nmos_rf
>>

Pins are added to the design. And we also refer to the <<RF_devices_guard_ring_drawn_guideline.pdf>> manual. But it seems the problem is still there.

The second problem is about the IND_SYM_CT device. DRC rules tell us that the top level metal should be departed from the inductor metal at least 50um. So we follow it to connect the plus and minus line of inductor device out with top layer metal. but the ind_sym_ct device can not be detected by calibre LVS. the report tells that "Corresponding cells could not be identified. Nothing in layout." Then we put vias on the inductor plus and minus line to steer the signal out through the metal underneath. But the ind_sym_ct device can not be detected by calibre LVS
either. So, how shall we connect the output terminal of the IND_SYM_CT device to steer the signal out.

Any reply will be greatly appreciated.

1# zhengwei_jimmy

very good article