做运放转换速率仿真时要加负载吗？
时间：10-02
整理：3721RD
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请问若要测试一运放的Slew Rate时要接负载吗?我在国外的某网站有个帖子是这样说的：
When simulating in cadence, connect out of the opa to the inverter "-", make sure the opa is a follower. put a large pulse signal to the noninverter "+" terminal and do transient analysis, then plot the out wave(of course,under the load u defined). at last, measure the slope of out voltage linear ramp, it is slew rate.
我不明白的是红色标注的部分。究竟要不要接上自己定义的负载才仿真呢?SR指标是不是在某一负载的条件下的?类似的问题，测试Settling time时 要不要接上负载呢?
When simulating in cadence, connect out of the opa to the inverter "-", make sure the opa is a follower. put a large pulse signal to the noninverter "+" terminal and do transient analysis, then plot the out wave(of course,under the load u defined). at last, measure the slope of out voltage linear ramp, it is slew rate.
我不明白的是红色标注的部分。究竟要不要接上自己定义的负载才仿真呢?SR指标是不是在某一负载的条件下的?类似的问题，测试Settling time时 要不要接上负载呢?
Yes, you must connect your defined capacitor load. It is because slew rate dv/dt = iout / c_load. It is the same for simulating settling time.
nmos做差分对时，SR-与CL有关，反之，SR+与CL有关
要加上负载，虽然负载较小时可能与负载关系不大，但还是应该是指定负载下的值。
国标一般是2K电阻
做运放不管做什么仿真,首先把负载加上(电容,如果驱动电阻,把等效电阻负载也加上)
这是前提
其实所有analog设计都一样,testbench一定要跟实际一样
要加的
负载应该加你这个电路的应用中可能有的最大负载，这样仿真出来的SR才有意义
仿真就应该尽量做到真吗
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