时钟恢复/产生电路，与频率合成器的区别？

Frequency synthesizers for RF applications
-system design consideration; phase noise, spur, and settling time
-integer-N/fractional-N frequency synthesizers
-direct digital frequency synthesizer
Clock-and-data recovery for serial link and optical communications
-system design considerations; jitter transfer, jitter tolerance, and jitter generation
-circuit design aspects in multi-Gb/s SerDes systems
-DLL-based CDR for serial-link backplane applications
-D/PLL-based CDR for SONET applications

agree！

In serial data communication, Clock and Data Recovery PLL is used to extracted clock signal from the transmitted data signal and use the extracted clock signal to synchronise reading of incoming data.In terms of phase/frequency detector design, this is very different from clock synthesis PLL.

thanks a lot！

顶一个先

楼上的正解啊

受教了，还是英文的