SSC removal

Hi, does anyone know how to demodulate the SSC effect embedded in the input clock to PLL? In PCIE1.1 specification, the input reference clock is modulated to be +/-300ppm due to SSC to avoid any EMI concern. If we ddin't de-modulate it properly, what will happen to our PLL?

Don't need demoulation. Actually, I don't think SSC is needed for PCIE 1.0.

thanks for pointing out. SSC feature may or may not be implemented due to platform level timing issue according to PCIE CEM 1.1 spec. If the reference clock supports spread spectrum clocking, any design challenge or concern applied to PLL to minimize the jitter?

Not really, the SSC is strictly well-defined. I remember it is 0~-5000ppm.Nothing specially except your PLL Loop can accomendate the headroom for the Vctrl.

how can i setup the simulation to test out if my PLL design can accommodate the SSC effect in reference input clock?

Or, what is the design criteria of the loop filter to reserve the headroom for Vctrl so that it can take in this reference clock with SSC effect? If SSC is about -5000ppm, is it similar to 0.5% frequency offset if reference clock is running at 100MHz