请教各位，如何提高pipelined adc的信噪比？

各位大虾，小弟正在做一个pipelined adc，设计目标是是12bit,100M，现在根据前仿的结构，信噪比只有60db左右，有效位为10左右，请问我该怎么来提高我电路的性能咯，提高信噪比?

有一定的设计参考给你么?指标已经很NB了

电路的等效输入噪声太大了，才导致snr只有60dB。如果电路的噪声已经足够小了，那么电路的thd就成为关键因素了。

pls tell us the basic info first such as VDD, VREF, Architecture(2.5b/stage or 1.5bit/stage etc...),otherwise it is too wide to talk about it.

pipelined adc with 1.5bit/stage,with vdd=3.3v ,smic0.13 .actually,i count the 60db with the cadence tools and excel.maybe 60db=snr+thd.but i just can't meet the request given by my boss.so ,i wantna to improve it.any help will appreciated！

how do you value the thermal noise as your performance?

then ,would you tell me how could i get the SNR or SINAD?