波形失真
时间：10-02
整理：3721RD
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本人刚刚学习fpga
用vhdl写了一个递减锯齿波 但波形失真 波形仿真如下
源码library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity signal2 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal2;
architecture a of signal2 is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
begin
if reset = '1'then
tmp:="11111111";
elsif rising_edge(clk)then
if tmp="00000000"then
tmp:="11111111";
else
tmp:=tmp-5;
end if;
end if;
q<=tmp;
end process ;
end a;
源码library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity signal2 is
port(clk,reset:in std_logic;
q:out std_logic_vector(7 downto 0));
end signal2;
architecture a of signal2 is
begin
process(clk,reset)
variable tmp:std_logic_vector(7 downto 0);
begin
if reset = '1'then
tmp:="11111111";
elsif rising_edge(clk)then
if tmp="00000000"then
tmp:="11111111";
else
tmp:=tmp-5;
end if;
end if;
q<=tmp;
end process ;
end a;