配置TLV320AIC3254的一些疑惑

TI的工程师们：

你们好！

最近在做学校的430项目，使用了TLV320AIC3254这款芯片，现在有如下疑惑；

1：

如果我对上面这个寄存器不配置，那么，内部的DAC是不是只能接受外部的I2S信号。而不能接受来自内部ADC的数据。要是我想接收内部ADC的数据，我是不是应该让D4=1，D5=0，实际上我是对I2S和内部ADC数据如何切换，并送给DAC不是很清楚。

2：下面是我写的配置代码，芯片作为从机接收外部I2S信号，播放声音，不知是否合理？

const TRegisterData Stereo_DAC_Playbackwith44_1kps[] =
{
//Assumption
//AVdd = 1.8V, DVdd = 1.8V
//The codec receives: MCLK = 11.2896 MHz,
//BLCK = 2.8224 MHz, WCLK = 44.1 kHz
//Ext C = 47uF
//Based on C the wait time will change.
//A higher or lower C value will require higher or lower for N
//Wait time = N*Rpop*C + 4* Offset ramp time
//Default settings used.
//PLL Disabled
//DOSR 128
//###############################################
//# Clock and Interface Settings
//# ---------------------------------------------
//# The codec receives: MCLK = 11.2896 MHz,
//# BLCK = 2.8224 MHz, WCLK = 44.1 kHz
//###############################################
{0x00, 0x00},//Select Page 0
{0x01, 0x01},//Initialize the device through software reset
{0x00, 0x00},//Select Page 0
{0X0B, 0X81},//NDAC = 1,dividers powered up
{0X0C, 0X82},//MDAC = 2,dividers powered up
{0X12, 0X01},//NADC = 1,dividers powered down
{0X13, 0X02},//MADC = 2,dividers powered down
//###############################################
//Configure Power Supplies
//###############################################
{0X00, 0X01},//Select Page 1
{0X02, 0X09},//Power up AVDD LDO**
{0X01, 0X08},//Disable Internal Crude AVdd in presence of external AVdd supply or before
//powering up internal AVdd LDO
{0X02, 0X01},//Enable Master Analog Power Control,Power up AVDD LDO
//Set full chip common mode to 0.9V
//HP output CM = 1.65V
//HP driver supply = LDOin voltage
//Line output CM = 1.65V
//Line output supply = LDOin voltage
{0X0A, 0X3B},

{0X47, 0X32},//Set the input power-up time to 3.1ms (for ADC)
{0X7B, 0X01},//Set the REF charging time to 40ms
//###############################################
//# Configure ADC Channel
//###############################################
{0X00, 0X01},//Select Page 1
{0X34, 0X80},//Route IN1L to LEFT_P with 20K input impedance
{0X36, 0X80},//Route CM1L to LEFT_M with 20K input impedance
{0X37, 0X80},//Route IN1R to RIGHT_P with 20K input impedance
{0X39, 0X80},//Route CM1R to RIGHT_M with 20K input impedance
//Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB
//since 20K input impedance is used single ended
{0X3B, 0X0C},
//Unmute Right MICPGA, Gain selection of 6dB tom ake channel gain 0dB
//since 20K input impedance is used single ended
{0X3C, 0X0C},
{0X00, 0X00},//Select Page 0
{0x51, 0xC0},//Power up LADC/RADC
{0X52, 0X00},//Unmute LADC/RADC
//###############################################
//# Configure DAC Channel
//###############################################
{0x00, 0x01},//Select Page 1
{0x14, 0x25},//De-pop: 5 time constants, 6k resistance
{0x0C, 0x08},//Route LDAC to HPL
{0x0D, 0x08},//Route RDAC to HPR
{0X0E, 0X08},//Route LDAC to LOL
{0X0F, 0X08},//Route RDAC to LOR
{0x09, 0X3C},//Power up HPL/HPR and LOL/LOR drivers***
{0X10, 0X00},//Unmute HPL driver, 0dB Gain
{0X11, 0X00},//Unmute HPR driver, 0dB Gain
{0X12, 0X00},//Unmute LOL driver, 0dB Gain
{0X13, 0X00},//Unmute LOR driver, 0dB Gain
{0X00, 0X00},//Select Page 0
{0X41, 0X00},//LDAC=>0dB
{0X42, 0X00},//RDAC=>0dB
{0X3F, 0XD6},//Power up LDAC/RDAC
{0X40, 0X04},//Unmute LDAC/RDAC
{0xFF, 0xFF}//结束
};

如果上电后不设置, 寄存器的值通常就是表中的复位值

谢谢，这个我知道。但是解决不了我的疑惑