关于TLV320AIC3254时钟配置
时间：10-02
整理：3721RD
点击：
如题
MCLK=12.288MHz;
P=1
R=1
J.D=7.3500
MDAC=4
NDAC=4
DOSR=128
BCLK-N=8
为什么产生的BCLK不是705.6KHz呢？
是哪里配置错了吗
我觉得手册是说明是没有错的, 好好验证一下你的设置, 再仔细看一下 TLV320AIC3254 Application Reference Guide SLAA408.
我已经看这手册很多遍了，也检查了我的配置很多遍，所以才到这里发帖子。。
哎。。真心塞
你好：
你是需要产生BCLK输出，是吧？然后你用的采样率是多少，48K还是44.1K。
你说一下的你的需求，晚点我帮你算一个系数吧。
嗯， 是的，采样率是44.1KHz，产生的BCLK是705.6KHz。MCLK是12.288MHz。非常感谢
忘记说了，量化位数是16bit
你现在产生的时钟是多少？你需要的是单声道的声音？
我没有示波器，测量不了，是单声道的声音。。。我算了很多个，只有一个成功，这是什么回事？难道使用手册有误？
你好：
这个配置行不通，因为BCLK=705.6K，采样率是44.1K，那么L+R的数据是16bit，也就是单通道数据只有8bit，这个是不行的，AIC3254只能支持16bit，24bit，32bit。
I2S协议也是立体声的时钟，不能支持你说的单通道。
我建议你降采样率。
你是不是把codec当做时钟芯片来用了，还是有什么特殊需求？
我需要的只是单声道，16bit数据，codec当做时钟芯片？我配置的只是MCLK = PLL_CLKIN，而其中MCLK针脚外接12.288MHz时钟源。。。I2S能配置成单声道的格式
Combined with the advanced PowerTune technology, the device can cover operations from 8 kHz mono
voice playback to audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio
and telephony applications.
Combined with the advanced PowerTune technology, the device can cover operations from 8 kHz mono
voice playback to audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio
and telephony applications.
这个怎么解释，难道我误解了其中的意思？
请教一下理论上单身道I2S信号，几个时钟和数据的时序波形？时序理解对了配置就比较简单了。
看了下I2S的标准，貌似并没有提到单声道，按我的理解，还是按双声道的时序发送数据，但只对其中一个声道发送数据。如果理解错误，请指正。。按这样理解的话，BCLK = world select length * 2 * samplebit = 44.1*2*16=1411.2K。按这样理理解，我配BCLK-N=4也没有改变效果，求解
你好：
是的，你的理解是对的。
配置没有效果的话，最有可能的是两个原因：
1.你设置的系数或者中间的时钟不在spec要求的范围内。
2.寄存器没有设置对。最明显的是BCLK和WCLK配置成output。
请问你是在我们EVM板上工作，还是你自己的板子？
非常感谢你的回答。
我是在自己的板子上实验的，我在i2s里，配置声卡为主模式，所以BCLK和WCLK必须为output啊，不然怎么工作呢？
我也检查了自己配置的参数，在specification里符合要求啊。。
你好：
你把你的配置代码带上注释，发上来看一下。
好的，英文写得可能不好，望见谅
void Inti_3254_TX()
{
int i;
unsigned char Reg[2];
unsigned char data[2];
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x01; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1); //self clear
for(i=0;i<100000;i++);
/*******************************************************************************************/
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x04; data[0]=0x03; I2C_Write_Data(0x30,Reg,1,data,1); //reg4 PLL_CLKIN = MCLK CODEC_CLKIN = PLL_CLK
//Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x05; data[0]=0x91; I2C_Write_Data(0x30,Reg,1,data,1); //reg5 PLL is power up //P is 1, R is 1
Reg[0]= 0x06; data[0]=0x07; I2C_Write_Data(0x30,Reg,1,data,1); //reg6 J is 7
Reg[0]= 0x07; data[0]=0x0d; data[0]=0xac; I2C_Write_Data(0x30,Reg,1,data,2); //reg7 D-val MSB is 13 //reg8 D-val LSB is 172
Reg[0]= 11; data[0]=0x84; data[1]=0x84; I2C_Write_Data(0x30,Reg,1,data,2); // NADC is power up , and N is 4 //MADC is power up, and M is 4
Reg[0]= 27; data[0]=0x0c; I2C_Write_Data(0x30,Reg,1,data,1); //reg27 BCLK is output
Reg[0]= 29; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1); //reg29 Bdiv_CLKIN = DAC_MOD_CLK
Reg[0]= 30; data[0]=0x84; I2C_Write_Data(0x30,Reg,1,data,1); //reg30 BCLK power up, BCLK-N is 4
/*************************************************************************************************************/
for(i=0;i<100000;i++);
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x3c; data[0]=0x08; I2C_Write_Data(0x30,Reg,1,data,1); //PRB_P8
Reg[0]= 0x00; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x01; data[0]=0x08; I2C_Write_Data(0x30,Reg,1,data,1);//Disabled weak connection of AVDD with DVDD
Reg[0]= 0x02; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);// Analog Blocks Enabled 1.72v
Reg[0]= 0x47; data[0]=0x32; I2C_Write_Data(0x30,Reg,1,data,1);//Analog inputs power up time is 6.4 ms
Reg[0]= 0x7b; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);// Reference will power up in 40ms //when analog blocks are powered up
for(i=0;i<10000;i++);
Reg[0]= 0x00; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);// page 1
Reg[0]= 0x14; data[0]=0x25; I2C_Write_Data(0x30,Reg,1,data,1);// Headphone amps power up slowly in 6.0 time constants // Headphone amps power up time is determined with 6K resistanc
// Left Channel DAC reconstruction filter's positive terminal is routed to HPL
// Right Channel DAC reconstruction filter's positive terminal is routed to HPR
Reg[0]= 0x0c; data[0]=0x08; data[1]=0x08; I2C_Write_Data(0x30,Reg,1,data,2);
// Left Channel DAC reconstruction filter output is routed to LOL
// Right Channel DAC reconstruction filter output is routed to LOR
Reg[0]= 0x0e; data[0]=0x08; data[1]=0x08; I2C_Write_Data(0x30,Reg,1,data,2);
// HPL is powered up
//HPR is powered up
// LOL is powered up
// LOR is powered up
Reg[0]= 0x09; data[0]=0x3c; I2C_Write_Data(0x30,Reg,1,data,1);
//page 0
Reg[0]= 0x10; data[0]=0x00; data[1]=0x00; I2C_Write_Data(0x30,Reg,1,data,2);
// NADC divider powered down * MADC divider powered down, ADC_MOD_CLK is same as DAC_MOD_CLK
// NADC=128 MADC=128
Reg[0]= 0x12; data[0]=0x00; data[1]=0x00; I2C_Write_Data(0x30,Reg,1,data,2);
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
//Left DAC Channel Digital Volume Control Setting -30dB
//Right DAC Channel Digital Volume Control Setting -30dB
Reg[0]= 0x41; data[0]=0xBC; data[1]=0xBC; I2C_Write_Data(0x30,Reg,1,data,2);
//Left DAC Channel Powered Up
// Right DAC Channel Powered Up
// Left DAC data Left Channel Audio Interface Data
// Right DAC data Right Channel Audio Interface Data
// Soft-Stepping is disabled
Reg[0]= 0x3f; data[0]=0xd6; I2C_Write_Data(0x30,Reg,1,data,1);
//Left DAC Channel not muted
// Right DAC Channel not muted
// Left and Right Channel have independent volume control
Reg[0]= 0x40; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
}
重新改下，方便看些
void Inti_3254_TX()
{
int i;
unsigned char Reg[2];
unsigned char data[2];
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x01; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1); //self clear
for(i=0;i<100000;i++);
/********************************PLL configure*****************************************/
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
//reg4 PLL_CLKIN = MCLK CODEC_CLKIN = PLL_CLK
Reg[0]= 0x04; data[0]=0x03; I2C_Write_Data(0x30,Reg,1,data,1);
//Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
//reg5 PLL is power up
//P is 1, R is 1
Reg[0]= 0x05; data[0]=0x91; I2C_Write_Data(0x30,Reg,1,data,1);
//reg6 J is 7
Reg[0]= 0x06; data[0]=0x07; I2C_Write_Data(0x30,Reg,1,data,1);
//reg7 D-val MSB is 13
//reg8 D-val LSB is 172
Reg[0]= 0x07; data[0]=0x0d; data[0]=0xac; I2C_Write_Data(0x30,Reg,1,data,2);
// NADC is power up , and N is 4
//MADC is power up, and M is 4
Reg[0]= 11; data[0]=0x84; data[1]=0x84; I2C_Write_Data(0x30,Reg,1,data,2);
//reg27 BCLK is output
Reg[0]= 27; data[0]=0x0c; I2C_Write_Data(0x30,Reg,1,data,1);
//reg29 Bdiv_CLKIN = DAC_MOD_CLK
Reg[0]= 29; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);
//reg30 BCLK power up, BCLK-N is 4
Reg[0]= 30; data[0]=0x84; I2C_Write_Data(0x30,Reg,1,data,1);
/*************************************************************************************************************/
for(i=0;i<100000;i++);
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x3c; data[0]=0x08; I2C_Write_Data(0x30,Reg,1,data,1); //PRB_P8
Reg[0]= 0x00; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);
Reg[0]= 0x01; data[0]=0x08; I2C_Write_Data(0x30,Reg,1,data,1);//Disabled weak connection of AVDD with DVDD
Reg[0]= 0x02; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);// Analog Blocks Enabled 1.72v
Reg[0]= 0x47; data[0]=0x32; I2C_Write_Data(0x30,Reg,1,data,1);//Analog inputs power up time is 6.4 ms
Reg[0]= 0x7b; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);// Reference will power up in 40ms //when analog blocks are powered up
for(i=0;i<10000;i++);
// page 1
Reg[0]= 0x00; data[0]=0x01; I2C_Write_Data(0x30,Reg,1,data,1);
// Headphone amps power up slowly in 6.0 time constants
// Headphone amps power up time is determined with 6K resistance
Reg[0]= 0x14; data[0]=0x25; I2C_Write_Data(0x30,Reg,1,data,1);
// Left Channel DAC reconstruction filter's positive terminal is routed to HPL
// Right Channel DAC reconstruction filter's positive terminal is routed to HPR
Reg[0]= 0x0c; data[0]=0x08; data[1]=0x08; I2C_Write_Data(0x30,Reg,1,data,2);
// Left Channel DAC reconstruction filter output is routed to LOL
// Right Channel DAC reconstruction filter output is routed to LOR
Reg[0]= 0x0e; data[0]=0x08; data[1]=0x08; I2C_Write_Data(0x30,Reg,1,data,2);
// HPL is powered up
//HPR is powered up
// LOL is powered up
// LOR is powered up
Reg[0]= 0x09; data[0]=0x3c; I2C_Write_Data(0x30,Reg,1,data,1);
//page 0
Reg[0]= 0x10; data[0]=0x00; data[1]=0x00; I2C_Write_Data(0x30,Reg,1,data,2);
// NADC divider powered down * MADC divider powered down, ADC_MOD_CLK is same as DAC_MOD_CLK
// NADC=128 MADC=128
Reg[0]= 0x12; data[0]=0x00; data[1]=0x00; I2C_Write_Data(0x30,Reg,1,data,2);
Reg[0]= 0x00; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
//Left DAC Channel Digital Volume Control Setting -30dB
//Right DAC Channel Digital Volume Control Setting -30dB
Reg[0]= 0x41; data[0]=0xBC; data[1]=0xBC; I2C_Write_Data(0x30,Reg,1,data,2);
//Left DAC Channel Powered Up
// Right DAC Channel Powered Up
// Left DAC data Left Channel Audio Interface Data
// Right DAC data Right Channel Audio Interface Data
// Soft-Stepping is disabled
Reg[0]= 0x3f; data[0]=0xd6; I2C_Write_Data(0x30,Reg,1,data,1);
//Left DAC Channel not muted
// Right DAC Channel not muted
// Left and Right Channel have independent volume control
Reg[0]= 0x40; data[0]=0x00; I2C_Write_Data(0x30,Reg,1,data,1);
}