AIC3254在“PurePath Wireless Configurator”中I2C配置寄存器P1_R9设置不成功

我们自己板子上，通过CC8530的“PurePath Wireless Configurator”（PWC）软件，I2C配置AIC3254寄存器，但唯独Page 1 / Register 9: Output Driver Power Control Register - 0x01 / 0x09 (P1_R9)设置为3F，AIC3254EVM-U CS中读出该寄存器的值为3C。但AIC3254EVM-U CS中可以正确设置该寄存器，即写入3F，读出也是3F，PWC中代码前后的寄存器都可以正确设置。不知什么原因？代码如下：

# PIN RESET
p Reset 1     # Release the reset pin
# RESET
w 30 00 00    # Select register page 0
w 30 01 01    # I2C reset
# CLOCK SETTINGS
w 30 0B 81    # Power up the NDAC divider with value 1
w 30 0C 82    # Power up the MDAC divider with value 2
w 30 0D 00    # Program OSR for DAC to 128 (MSB)
w 30 0E 80    # Program OSR for DAC to 128 (LSB)
w 30 12 81    # Power up the NADC divider with value 1
w 30 13 82    # Power up the MADC divider with value 2
w 30 14 80    # Program OSR for ADC to 128
# DIGITAL INTERFACE
w 30 1B 00    # I2S, 16-bit, BCLK and WCLK are inputs
# PROCESSING BLOCK USAGE
w 30 3C 08    # Select DAC processing block PRB_P8
w 30 3D 01    # Select ADC processing block PRB_R1
# ANALOG POWER SUPPLY
w 30 00 01    # Select register page 1
w 30 01 08    # Disable internal crude AVDD before powering up the internal AVDD LDO
w 30 02 01    # Enable internal analog LDO, analog blocks powered
w 30 0A 40    # Common mode set to 0.75V 
# MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP
w 30 47 31    # MICPGA startup delay is 3 ms
w 30 7B 01    # Reference charging time is 40 ms
w 30 14 65    # HP driver power-up: 50 ms soft routing step time, 5.0 time constants, 6k resistance
# AUDIO ROUTING
w 30 0C 0C    # HPL routing: Left channel's DAC reconstruction filter's positive terminal
w 30 0D 0C    # HPR routing: Right channel's DAC reconstruction filter's positive terminal
w 30 0E 0A    # LOL routing: Left channel's DAC reconstruction filter output
w 30 0F 0A    # LOR routing: Right channel's DAC reconstruction filter output
w 30 00 00
w 30 3F D4 
w 30 00 01
w 30 34 40    # IN1L is routed to Left MICPGA with 10K resistance
w 30 36 40    # CM1L is routed to Left MICPGA via CM1L with 10K resistance
w 30 37 40    # IN1R is routed to Right MICPGA with 10K resistance
w 30 39 40    # CM1R is routed to Right MICPGA via CM1R with 10K resistance
w 30 09 3F
w 30 00 00
w 30 40 00 
# DC FILTER LEFT CHANNEL
w 30 00 08    # Select register page 8
w 30 18 7F    #                n0 + n1 * z^-1
w 30 19 FF    #     H(z) = ----------------------
w 30 1A 00    #               2^23 - d1 * z^-1
w 30 1C 80    #
w 30 1D 01    # The constants are defined as
w 30 1E 00    #     n0 = 32767 * 256
w 30 20 7F    #     n1 = -32767 * 256
w 30 21 FC    #     d1 = 32768 * 256 * (1- 2^13)
w 30 22 00    # This gives a filter with cutoff at approx. 1 Hz
# DC FILTER RIGHT CHANNEL
w 30 00 09    # Select register page 9
w 30 20 7F    #                n0 + n1 * z^-1
w 30 21 FF    #     H(z) = ----------------------
w 30 22 00    #               2^23 - d1 * z^-1
w 30 24 80    #
w 30 25 01    # The constants are defined as
w 30 26 00    #     n0 = 32767 * 256
w 30 28 7F    #     n1 = -32767 * 256
w 30 29 FC    #     d1 = 32768 * 256 * (1- 2^13)
w 30 2A 00    # This gives a filter with cutoff at approx. 1 Hz

谢谢！

由于我没有EVM板，我无法帮你重现，既然可以使用AIC3254EVM-U CS修改，可能是软件的BUG。