DS90UB913芯片问题咨询

1、ds90ub913a-q1.pdf中16页处

• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.

这个限制是什么意思,为什么会有这个限制？

2、ds90ub913a-q1的mode选择（12-bit HF/LF， 10-bit）是不是根据DES的mode来决定的。

1. 这个问题在e2e上也有客户咨询过，10bit HS/VS受限的原因：The data inputs are sampled on each PCLK and those data bits are encoded onto the FPD-III words which are being sent out.   HSYNC and VSYNC are much lower bandwidth, and therefore do not need to be sampled and transmitted as quickly as the other data bits.   This results in the restriction to have no more than one transition every 10 PCLK cycles.   If you want to send a high bandwidth signal across the link, you may be able to do so using 12 bit mode, and using the extra two data bits to transmit the timing information.

2. ds90ub913a-q1的mode的选择是寄存器0x05 的bit[3:2]控制的。可以看下datasheet中的register map。