时钟PLL Lock问题和560仿真器-233错误

3568.cdce62005.pdf

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

C:\DOCUME~1\ADMINI~1\LOCALS~1\APPLIC~1\.TI\
1508484825\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'seed560v2u.out'.
The library build date was 'May 30 2012'.
The library build time was '23:17:26'.
The library package version is '5.0.747.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.

An error occurred while hard opening the controller.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.

[End]

Andy，您好

最近用XDS560仿真器连接6678，按照开发板自行设计的板子，测试连接时候出现上述错误，连接开发板时候一切正常，测试了一下，发现时钟芯片PLL lock输出端的电压不是3.3V，也就是时钟没有锁定，时钟电路见附件。请问这是硬件设计出问题了吗，这个和gel文件应该没有什么关系吧？

从你描述看来是CDCE62005没有配置好。检查一下PLL的配置代码，确定配置命令写成功了

您好，Dylan，现在可以确定的是时钟信号100MHZ核时钟，66.7MHZ DDR时钟都是正确的，电源信号也测试正常，接上仿真器后仍然是连接不上，产生上述同样的错误提示。我们用的是开发板上的那个560仿真器，电路板是自己按照开发板设计的。请问，开发板上面有8个供电信号560V2 PWR1，有个XDS560_IL信号，是什么信号呢？我用示波器测的好像是010101之类的信号，具体是什么信号呢？期待您的回复。谢谢

XDS560_IL信号是用来给 XDS560V2 供电的，我看了下， XDS560V2 仿真器好像也只能给TMDXEVM6678LE - TMS320C6678 Lite Evaluation Module开发板用。

那个60PIN的接口和开发板上面是一样的，然后我们单独做一个5V，3.3V加上XDS560_IL信号，这样可以使用这个仿真器吗？