利用FPGA和DP83640接口问题
请问专家我想用FPGA实现DP83640的IEEE1588时钟接口，在硬件电路上应怎么设计，需要哪些信号线与FPGA连接，采用RMII模式。有DP83640的IEEE1588软件设计相应的参考资料吗？另外DP83630和DP83640有什么区别呢？
1)RMII:
— TX_EN
— TXD[1:0]
— RX_ER (optional for MAC)
— CRS/CRS_DV
— RXD[1:0]
— X1 (25 MHz in RMII Master mode, 50 MHz in RMII Slave
mode)
— RX_CLK, TX_CLK, CLK_OUT (50 MHz RMII reference
clock in RMII Master mode only)
2)参考软件请从下面网页下载。
www.ti.com/.../dp83640sw-lib
3)dp83630 belong to mini phy, have small LLP package. sp83640 full function
谢谢你的回答，也就是说将所有的这些线都要接到FPGA的IO脚？我如果将RMII口分别接到处理器CPU,和FPGA，信号线并联，用CPU实现网络通讯功能，FPGA只是实现IEE1588时钟对时功能，这样做可以吗？
谢谢你的回答，也就是说将所有的这些线都要接到FPGA的IO脚？我如果将RMII口分别接到处理器CPU,和FPGA，信号线并联，用CPU实现网络通讯功能，FPGA只是实现IEE1588时钟对时功能，这样做可以吗？
一般DP83640 只会连接一个mac。连接MCU或FPGA。不会连两个。
您好，关于您说的第二点参考软件，这个参考软件是不是必须连接到demo板才能工作。还有，有没有这个软件的使用说明？看里边的说明看晕了。。。
您好，请问这个RX_CLK\、TX_CLK、CLK_OUT和stm32之间怎么接的，接普通IO口就行了吗，我看手册上说貌似CLK_OUT是用来做测试用的，跪谢
您好，请问这个RX_CLK\、TX_CLK、CLK_OUT和stm32之间怎么接的，接普通IO口就行了吗，我看手册上说貌似CLK_OUT是用来做测试用的，跪谢，邮箱sxx2962458@126.com，或加我QQ602668820，谢谢大神
RX_clk: output pin,
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for
100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally generated
50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
TX_CLK: output pin.
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode
or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. The
MAC should source TX_EN and TXD[3:0] using this clock.
RMII MODE: Unused in RMII Slave mode. The device uses the X1
reference clock input as the 50 MHz reference for both transmit and
receive. For RMII Master mode, the device outputs the internally generated
50 MHz reference clock on this pin.
This pin provides an integrated 50 ohm signal termination, making external
termination resistors unnecessary.
Clk_out
CLOCK OUTPUT: This pin provides a highly configurable system clock,
which may have one of four sources:
1. Relative to the internal PTP clock, with a default frequency of 25 MHz
(default)
2. 50 MHz RMII reference clock in RMII Master Mode
3. 25 MHz Receive Clock (same as RX_CLK) in 100 Mb mode
4. 25 MHz or 50 MHz pass-through of X1 reference clock
CLOCK INPUT: This pin is used to input an external IEEE 1588 reference
clock for use by the IEEE 1588 logic. The CLK_OUT_EN strap should be
disabled in the system to prevent possible contention. The PTP_CLKSRC
register must be configured prior to enabling the IEEE 1588 function in
order to allow correct operation.
这段我 在手册上也看到了，请问可以说的明白点吗，这三个引脚是干嘛的，手册我不大看的懂，谢谢
手册上说的很详细了，我给你邮件讨论。
您好，我也遇到上述问题，能否邮箱联系？zm_wh2007@126.com，谢谢
看到你的帖子，我也在做DP83640，望交流QQ:79578133