多块DAC38J84之间的延时差如何控制在100ps左右？

最近我们评估一个项目，要使用多块DAC38J84，采样速率1Gsps，但要保证所有DAC38J84芯片之间，最后的数据输出之间的延时差在100ps左右。这个指标要求很严，不知道大家有没有这样的解决方案？谢谢！

这个器件为了应对这个方面的要求, 专门设计了 多芯片同步模式. 可以详细研究一下

7.3.8 Multi-Device Synchronization
In many applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely synchronized such that their outputs are phase aligned. DAC37J84/DAC38J84 achieves the deterministic latency using SYSREF (JESD204B Subclass 1).
SYSREF is generated from the same clock domain as DACCLK, and is sampled at the rising edges of the device clock. It can be periodic, single-shot or “gapped” periodic. After having resynchronized its local multiframe clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the signal on the SYSREF input can be enabled and disabled via the SPI interface.

你好，DAC38J84的Multi-Device Synchronization就是专门针对多天线同步而设计的。推荐你使用该器件及按照jesd204b标准，谢谢。

谢谢您的解答！MIMO通道（多天线收发）之间的延时要求一般在几十ns范围内都可以，此芯片固然不存在问题。但我们的指标要求是100ps左右，JESD204B我查看过，但我对于能否达到这个指标还是感到担心，不知道有没有这样的实验案例。