关于TLC3548驱动问题
纠结几天的AD还是调不出来,,一开始基准电源接反了。。后来改过来了。。还是调不出来。希望有了解此芯片的给解答下
采用SPI接口
write_3548(0xa000);
Delay_ms(1);
write_3548(0xa800);
while(1)
{
Delay_ms(1);
for(i=0;i<16;i++)
{
write_3548(0x5000);
Delay_ms(10);
result[i]=read_3548();
}
}
子程序:
void write_3548(unsigned int cmd)
{
TLC3548_CS_L;
delay_us(100);
SpiB0_WriteData(cmd>>8);
SpiB0_WriteData(0xFF&cmd);
delay_us(100);
TLC3548_CS_H;
}
unsigned int read_3548(void)
{
unsigned char h=0,l=0;
unsigned int advalue;
TLC3548_CS_L;
delay_us(100);
h=SpiB0_WriteData(0x70);
l=SpiB0_WriteData(0x00); //继续发送数据,增加时钟,收取正确的数据
delay_us(100);
TLC3548_CS_H;
advalue=((unsigned int)h<<8)|l;
advalue=advalue>>2;
return advalue;
}
能收到数据,但是不对。
讲讲收到的数据有啥不对, 是不是错位了一位
这种情况往往是 SPI 初始化里的 CLK 时钟和波形设置错位引起的.
根据手册的时序波形, 再仔细研究一下.
是这样的,当运行
write_3548(0xa000);
时,得到一个数据。这个数据是个随机的,每次断电重新上电得到的都是不一样的
继续运行
Delay_ms(1);
write_3548(0xa800);
以及后来的3548写动作。。收到的都是前面的一样的数据。
TLC3548的要求是:
The host microprocessor is set as the SPI master with CPOL = 0 (active high clock), and CPHA = 1 (transmit
data is clock out at rising edge of CLK, receive data are sampled at falling edge of CLK). 16 bits (or more) per
transfer is required.
我用的430单片机对应的位
UCCKPH Bit 7 Clock phase select.
0 Data is changed on the first UCLK edge and captured on the following edge.
1 Data is captured on the first UCLK edge and changed on the following edge.
UCCKPL Bit 6 Clock polarity select.
0 The inactive state is low.
1 The inactive state is high.
我设的是UCCKPH为1,UCCKPL为0.
不知道对不对,,也试过其他设置,,也不行啊
好揪心啊。。项目好急啊。。
我有仔细的看了看,问题解决了。。。在发送配置的时候,,应该选择短周期采样。。而不是原先选的长周期采样