ADS8364数据转换

0042.ADS8364硬件电路.pdf我用ADS8364和FPGA做一个电压的采样电路。硬件电路如PDF上的。程序如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aa is
port (rst,clk,adeoc:in std_logic;
      adb:in std_logic_vector(15 downto 0);
      adclk,adrd,adwr:out std_logic;
      hold:out std_logic_vector(2 downto 0);
      ada:out std_logic_vector(2 downto 0);
      led1:out std_logic_vector(4 downto 0);
      led2:out std_logic_vector(15 downto 0);
      led:out std_logic);
end aa;
architecture behav of aa is
constant s0    :std_logic_vector(12 downto 0):="0000001100000";--启动转换 
constant s1    :std_logic_vector(12 downto 0):="1110001100001";--进入17个周期等待转换结束，不检测EOC 
constant s2    :std_logic_vector(12 downto 0):="1110001100010"; 
constant s3    :std_logic_vector(12 downto 0):="1110001100011"; 
constant s4    :std_logic_vector(12 downto 0):="1110001100100"; 
constant s5    :std_logic_vector(12 downto 0):="1110001100101"; 
constant s6    :std_logic_vector(12 downto 0):="1110001100110"; 
constant s7    :std_logic_vector(12 downto 0):="1110001100111"; 
constant s8    :std_logic_vector(12 downto 0):="1110001101000"; 
constant s9    :std_logic_vector(12 downto 0):="1110001101001"; 
constant s10   :std_logic_vector(12 downto 0):="1110001101010"; 
constant s11   :std_logic_vector(12 downto 0):="1110001101011"; 
constant s12   :std_logic_vector(12 downto 0):="1110001101100"; 
constant s13   :std_logic_vector(12 downto 0):="1110001101101"; 
constant s14   :std_logic_vector(12 downto 0):="1110001101110"; 
constant s15   :std_logic_vector(12 downto 0):="1110001101111"; 
constant s16   :std_logic_vector(12 downto 0):="1110001110000"; 
constant s17   :std_logic_vector(12 downto 0):="1110001110001"; 
constant s18   :std_logic_vector(12 downto 0):="1110001110010"; 
constant s19   :std_logic_vector(12 downto 0):="1110000110011";--读ch1数据 
constant s20   :std_logic_vector(12 downto 0):="1110011110100"; 
constant s21   :std_logic_vector(12 downto 0):="1110010110101";--读ch2数据 
constant s22   :std_logic_vector(12 downto 0):="1110101110110"; 
constant s23   :std_logic_vector(12 downto 0):="1110100110111";--读ch3数据 
constant s24   :std_logic_vector(12 downto 0):="1110111111000"; 
constant s25   :std_logic_vector(12 downto 0):="1110110111001";--读ch4数据 
constant s26   :std_logic_vector(12 downto 0):="1111001111010"; 
constant s27   :std_logic_vector(12 downto 0):="1111000111011";--读ch5数据 
constant s28   :std_logic_vector(12 downto 0):="1111011111100"; 
constant s29   :std_logic_vector(12 downto 0):="1111010111101";--读ch6数据 
constant s30   :std_logic_vector(12 downto 0):="1110001111110";
signal clk_ad :std_logic;

signal Q: std_logic_vector(12 downto 0);
signal clkcnt  : std_logic_vector(16 downto 0);
signal readst:std_logic_vector(4 downto 0);
signal ch1,ch2,ch3,ch4,ch5,ch6:std_logic_vector(15 downto 0);
begin
process(rst,clk) is
begin
if rst='0' then
clkcnt <= "00000000000000000";
elsif(clk'event and clk = '1') then
if(clkcnt = "11111111111111111") then
clkcnt<= "00000000000000000";
else
clkcnt <= clkcnt+1;
end if;
end if;
end process;

adclk <= clkcnt(15);
clk_ad<= clkcnt(15);
led<=clk_ad;
COM:process(clk_ad,rst)
begin
if rst='0' then
    Q<=s0;
elsif clk_ad'event and clk_ad='1' then
case  Q is
    when s0=>Q<=s1;
    when s1=>Q<=s2;
    when s2=>Q<=s3;
    when s3=>Q<=s4;
    when s4=>Q<=s5;
    when s5=>Q<=s6;
    when s6=>Q<=s7;
    when s7=>Q<=s8;
    when s8=>Q<=s9;
    when s9=>Q<=s10;
    when s10=>Q<=s11;
    when s11=>Q<=s12;
    when s12=>Q<=s13;
    when s13=>Q<=s14;
    when s14=>Q<=s15;
    when s15=>Q<=s16;
    when s16=>Q<=s17;
    when s17=>Q<=s18;
    when s18=>Q<=s19;
    when s19=>Q<=s20;
    when s20=>Q<=s21;
    when s21=>Q<=s22;
    when s22=>Q<=s23;
    when s23=>Q<=s24;
    when s24=>Q<=s25;
    when s25=>Q<=s26;
    when s26=>Q<=s27;
    when s27=>Q<=s28;
    when s28=>Q<=s29;
    when s29=>Q<=s30;
    when s30=>Q<=s0;
    when others=>Q<=s0;
 end case;
 hold<=Q(12 downto 10);
 ada<=Q(9 downto 7);
 adrd<=Q(6);
 adwr<=Q(5);
 readst<=Q(4 downto 0);
 end if;

 end process;
process(clk,readst)
begin
 if(clk'event and clk='1')then
  if readst="10011" then
   ch1 <= adb(15 downto 0); led2<=ch1;
     elsif readst="10101" then
      ch2 <= adb(15 downto 0);-- led2<=ch2;
  elsif readst="10111" then
      ch3 <= adb(15 downto 0);-- led2<=ch3;
  elsif readst="11001" then
      ch4 <= adb(15 downto 0); --led2<=ch4;
  elsif readst="11011" then
      ch5 <= adb(15 downto 0); --led2<=ch5;   
  elsif readst="11101" then
      ch6 <= adb(15 downto 0);-- led2<=ch6;
  else
      ch1<="0000000000000000";
      ch2<="0000000000000000";
      ch3<="0000000000000000";
      ch4<="0000000000000000";
      ch5<="0000000000000000";
      ch6<="0000000000000000";     
  end if;
 end if;
end process;
 end behav;
  但输出数据似乎误差很大。求指教！有懂得帮忙看看，是否有错吗？

我现在只使CH1的数据输出。

1. EOC是个输出脚，不一定能走大电流，把LED拆掉，让EOC直接连到FPGA的GPIO上。

2. CS恒低可能有风险，建议拉到FPGA的SPI口，用程序控制。

3. 几个SGND只是连接到一起打了一个GND的label，是否在实际的PCB上连接到地了？

4. 建议先跑一个通道，输入固定值，比如输入1/2 Full scale，先把采直流调通。

5. 手册第4页所示，输出格式是2的补码，检查一下程序上有没有把补码按照偏移码处理了。