关于ths8200的时钟问题

          最近在配置dm6467+ths8200的VGA输出，ths8200输入20bit ，4：2：2 ，Ycbcr，准备输出XVGA 1280X1024，108Mz。按照ti给出的配置文件，配置ths8200的寄存器。但是没有显示，显示器提示“超出显示范围”，用示波器测试发现HS_OUT只有49Khz，VS_OUT只有50Hz。正常值HS_OUT应该为64.10KHZ，VS_OUT应该为60.24HZ。个人检查了好几遍寄存器，没有发现任何问题。请问，会是什么原因呢？

          对ths8200的配置有如下疑问：

          1，我的HS_IN与VS_IN没有使用，3.3V上拉。FIDIN也没有使用，接地下拉。请问这样处理是否正确？

          2，ths8200的时钟用的是VPIF的输入时钟，峰峰值为2.6V，而不是一般有源晶振的5-6V，请问这对ths8200有影响么。

          望不吝赐教，谢谢！

哦  ti关于SXGA60HZ-108M的寄存器配置文件如下  我检查了很多遍  我的配置和ti的一模一样。。。。

BEGIN_DATASET  // Appended by WinVCC4 v4.50a.  Saved all registers.

DATASET_NAME,"THS8200_SXGA60Hz-108MHz  ( 20 bit 4:2:2, embedded)  HS/VSout +/+, YCbCr>RGB"

//THS8200//////////////////////////////////
WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl           
WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1           
WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1           
WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3           
WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3           
WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1           
WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1           
WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2           
WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2           
WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1        
WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12       
WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23       
WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3        
WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl  20bit 422
//sync tip and horizontal blank level setup        
WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
WR_REG,THS8200,0x01,0x23,0x2A // dtg_y_sync_upper   
WR_REG,THS8200,0x01,0x24,0x00 // dtg_cbcr_sync_upper
//horizontal timing setup
WR_REG,THS8200,0x01,0x25,0x70 // dtg_spec_a   112      
WR_REG,THS8200,0x01,0x26,0x2E // dtg_spec_b       48-2  
WR_REG,THS8200,0x01,0x27,0x00 // dtg_spec_c         
WR_REG,THS8200,0x01,0x28,0x68 // dtg_spec_d         360
WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
WR_REG,THS8200,0x01,0x2A,0x00 // dtg_spec_e         
WR_REG,THS8200,0x01,0x2B,0x80 // dtg_spec_h_msb     
WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb     
WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb     
WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb     
WR_REG,THS8200,0x01,0x2F,0x2E // dtg_spec_k_lsb    48-2 
WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb     
WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1        
WR_REG,THS8200,0x01,0x32,0x00 // dtg_speg_g_lsb     
WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb     
WR_REG,THS8200,0x01,0x34,0x06 // dtg_total_pixel_msb //1688 pixels
WR_REG,THS8200,0x01,0x35,0x98 // dtg_total_pixel_lsb
WR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb    
WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    
WR_REG,THS8200,0x01,0x38,0x89 // dtg_mode  Generic SDTV        
WR_REG,THS8200,0x01,0x39,0x44 // dtg_frame_field_msb //1066 lines
WR_REG,THS8200,0x01,0x3A,0x2A // dtg_frame_size_lsb 
WR_REG,THS8200,0x01,0x3B,0x2A // dtg_field_size_lsb 
WR_REG,THS8200,0x01,0x3C,0x80 // dtg_vesa_cbar_size 
//CSM setup to map YCbCr to FS RGB        
WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high  
WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high  
WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb   
WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb   
WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode           
 
//Generic Mode Line Type Setup. Set dtg_bp 2_msb and lsb to 1067 (lines per frame +1) 
WR_REG,THS8200,0x01,0x50,0x04 // dtg_bp1_2_msb     /////////////// /
WR_REG,THS8200,0x01,0x58,0x00 // dtg_bp1_lsb        
WR_REG,THS8200,0x01,0x59,0x2B // dtg_bp2_lsb          /////////////////////  
       
WR_REG,THS8200,0x01,0x68,0x00 // dtg_linetype1  = active video
WR_REG,THS8200,0x01,0x69,0x00 // dtg_linetype2   = active vieo   

WR_REG,THS8200,0x01,0x70,0x70 // dtg_hlength_lsb     //112
WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb       
WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb       
WR_REG,THS8200,0x01,0x73,0x04 // dtg_vlength_lsb    
WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
WR_REG,THS8200,0x01,0x7A,0x58 // dtg_hs_in_dly_lsb   40+Hfp = 40+48=88
WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
WR_REG,THS8200,0x01,0x7C,0x01 // dtg_vs_in_dly_lsb  
WR_REG,THS8200,0x01,0x82,0x3B // embedded syncs and pol_cntl   +HS +VS

END_DATASET

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