DAC8728输出问题

DAC8728必须要在cs信号为高的时候才输出么？说明文档40面里面说到 异步模式 When the correction engine is off (SCE bit = '0'), the DAC Data Registers and DAC latches are updated immediately when CS goes high.                       cs是片选信号，低有效，片选为高了，芯片都不工作了，怎么还输出？

还有个问题，文档里面说  Asynchronous Mode ：In this mode, the LDAC pin is set low at power-up.    Synchronous Mode：To activate this mode, take LDAC low or set the LD bit to '1' after CS goes high. 我就设置LDAC一直低，那不矛盾么，到底是异步还是同步？

你好！

第一个问题：在CS上升之后，其实存在一个时间t7，可以参考figure3和figure 4，t7即为Delay from CS rising to data change。

第二个问题: If asynchronous mode is desired, LDAC must be permanently tied low before power is applied to the device. If synchronous mode is desired, LDAC must be logic high during power-on.

从上面两个单词可以看到，一个是逻辑可控的，一个是固定的，所以是不矛盾的。