ADS1240 power consumption test

Hi

We'd like to use the ADS1240 in our design and want to know it's power consumption in power down mode.

We do a test with following setup:

DVDD connected to 3.3V and AVDD / Vref is open.

The PDN pin is connected to ground to force the device in power down mode.

Crystal is not soldered, i.e., no clock input to the chip.

All other I/O and control pins are left open.

We measure the digital current, it is around 80uA and varies as we touch the device.  It is quite different from the datasheet where it should be 0.5nA.

We don't know whether our test setup is correct or not, could you please provide us your test circuit for digital current and analog current measurement in power down mode?

Thanks!

Sibing

Please apply TI free sample for another testing to make sure whether the chips which you have quality  issue.

I  tested the ADS1240 sample, then I get the ADS1241 EVM Board, and I get the same result with you. I guess that you test the PDWN curret by fluke.

  Part of the problem may be due to the test meter you are using.  In characterization a HP/Agilent 3458A is used.  The ADS1241MEVM was designed so that you can make direct current measurements connecting the meter to J4 (pins 3 and 4.)  One thing to consider is that the cap (C18 on the EVM) may interfere with the measurement.  You may have to wait for the measurement to settle and there may also be some leakage.  Another thing to remember is that all digital signal pins must connect to something.  If left floating, excessive current may be drawn through the device in an indeterminate state (cross over region where both NMOS and PMOS transistors are conducting.)

  So the test method involves making sure that you have a meter capable of measuring sub nanoamps, remove (or consider the effect of) any device that is also connected to the same current path of the ADS1240, and make sure that all digital pins are connected properly (RESET should be high.)