Verilog实现关于24位输出的并串转换输出，附代码以及modelsim的仿真图。

这个是我的代码
module shifter(din,clk,reset,dout,load);
input [23:0]din;
input load;
input clk;
input reset;
outputdout;
reg [23:0] data_buf;

always @ (posedge load)
begin
data_buf <= din;
end

always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data_buf<=24'b0;
else
begin

data_buf<=data_buf<<1;
end
end

assign dout=data_buf[23];

endmodule

`timescale 1ns/1ns
module t;
reg clk,reset;
reg [5:0] rptr;
regsigned [23:0] sindat[0:64];
integer file;
wire dout;
reg [23:0] din;
reg load;

initial
begin
$readmemb("shift.dat",sindat);
end
//export the waveform
initial
begin
file=$fopen("shift.txt","w");
end
always @(posedge clk)
begin
$fwrite(file,"%d\n",t.m.dout);
end
//The main block, generate the stimulus
always @(posedge load)
begin
rptr<=rptr + 1;
end
always @(posedge load)
begin
if (reset ==1'b1)
din <= 0;
else
din <= sindat[rptr];//the filter_in has 4-bit-width
end

initial
begin
rptr =0;
clk=1;
load=0;
reset=0;
#40 reset = 1;
#20 reset = 0;
#60 load= 1;
#20 load= 0;

#(127*40+20) load =1;
#20 load= 0;
#(127*40+20) load =1;
#20 load= 0;
#(127*40+20) load =1;
#20 load= 0;
#(20 * 1000) $stop;
end

always #(20) clk=~clk;


shifter m(.din(din),.dout(dout),.clk(clk),.load(load),.reset(reset));
endmodule

上面是testbench~

always @ (posedge load)
begin
data_buf <= din;
end
这个看起来就很别扭

我建议用个计数器吧，每次时钟沿一来，传一位出去，并且计数器加1.eg:
data_buf<=data_buf [NUM];
NUM <= NUM +1'b1;
if(NUM==5'd24) begin
NUM <= 5'd0;
end

学习，学习！

你的load信号出来时din没有准备好，当然每次采样都是上一次的数据了。

谢谢6楼，有个计数器是要好一些。现在想想其实要是用FSM可能更好控制一点吧

谢谢你的回复，那么我想请教一下需要怎么修改呢?

suiji
我想问一下，一般这种问题需要怎么修改的呢

很好
大家继续发扬

bucuo,zhengxuyao