"wire A ;" error

i declare a variable as "wire [31:0] A [1:0];" in my verilog code,
but it reports an error:"expect a comma".
is there something wrong with my declaration ? a reg type ?
or
other verilog codes cause the error ?
plz help me and thanks in advance！

you want 2-d array or ?

试着用verilog 和 ncverilog 分别编译看看报出来的结果一样不?

wire型没有二维数组的形式

wire没有这种形式吧，reg才可以

对应到硬件上来说小编这样写相当于想在一根导线上传输两个电平吧?