微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > 大家看看程序什么地方错了阿?

大家看看程序什么地方错了阿?

时间:10-02 整理:3721RD 点击:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY disp IS
PORT(clk:IN STD_LOGIC;
clka:IN STD_LOGIC;
addr:INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
data:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE disp_arch OF disp IS
TYPE romtable IS ARRAY (0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
CONSTANT roma:romtable:=romtable'(
"11101111",
"00000001",
"01101101",
"00000001",
"01101101",
"00000001",
"11101111",
"11100001");
CONSTANT romb:romtable:=romtable'(
"00000000",
"11111101",
"11111011",
"00000000",
"11110111",
"11110111",
"11110111",
"11100111");
SIGNAL q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
P1ROCESS(clka)
BEGIN
IF rising_edge(clka)THEN
q<=q+'1';
END IF;
END PROCESS P1;
P2ROCESS(clk)
BEGIN
IF rising_edge(clk)THEN
addr<=addr+'1';
END IF;
END PROCESS P2;
P3ROCESS(addr)
BEGIN
IF q(3)='1' THEN
data<=roma(addr);
ELSE
data<=romb(addr);
END IF;
END PROCESS P3;
END disp_arch;

程序完成什么功能?为什么有两个时钟?如何出错?

就是你写清楚一点阿

大概介绍
大概介绍以下,老大

两个异步时钟逻辑最后集中到一个组合逻辑输出复选上,将会造成毛刺和大量冲激,输出结果可能非稳定!

再定义一个integer型信号tmp,讲addr 从std_logic_vector 转成 integer后赋给 tmp
在最后一个进程里用 tmp替代 addr
程序的主要问题是信号类型的问题
rom() 里只能填整数型信号

提供一段代码供lz参考
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity myduram is
generic (width:integer;
depth: integer;
addrw:integer);
port(datain:in std_logic_vector(width-1 downto 0);
dataoutut std_logic_vector(width-1 downto 0);
clock_w,clock_r:in std_logic;
we,re:in std_logic;
wadd:in std_logic_vector(addrw-1 downto 0);
radd:in std_logic_vector(addrw-1 downto 0));
end myduram;
architecture art of myduram is
type mem is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal ramtmp:mem;
constant zs64: std_logic_vector(width-1 downto 0):=(others=>'Z');

begin
process(clock_w,we)
begin
if(clock_w'event and clock_w='1')then
if(we='1')then
ramtmp(conv_integer(wadd))<=datain;
end if;
end if;
end process;
process(clock_r,re)
begin
if(clock_r'event and clock_r='1')then
if(re='1')then
dataout<=ramtmp(conv_integer(radd)) ;
elsenull;
end if;
end if;
end process;
end art;

是编译不过去还是功能实现有问题(比如有毛刺等)?

六楼的说得很对,如果只是编译通不过的话

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top