新手求助一个关于VHDL编程的问题

我编写了下列程序，想实现在dataout信号的下降沿时对信号a复值，但这些信号都是在时钟的上升沿采样的。但出现了下列的错误提示，应该怎样写呢?
process(clock)
begin
if clock'event and clock='1' then
if dataout'event and dataout='0' then
a<='1';
else
a<=b;
end if;
end if;
end process p1;
Error: VHDL error at wc.vhd(23): can't infer register for signal "a" because signal does not hold its value outside clock edge

architecture behav of your_design is

signal tmp: std_logic;存储dataout的副本
signal dataout_rise: std_logic; dataout的下降沿脉冲
begin
process(clock)
begin
if clock'event and clock='1' then
if （dataout_rise＝'1'） then
a<='1';
else
a<=b;
end if;
end if;
end process p1;
process（clock）
begin
if clock'event and clock='1' then
tmp <=dataout;
end if;
end process;
dataout_rise<='1' when (dataout='0' and tmp='1') else
'0';
end behav;

谢谢小编！

真的很好哈，很巧妙！~