工程仿真是正确的，但是时序仿真没有输出，帮忙！

我是刚刚开始作FPGA的新手，好不容易学会时序仿真了，但是时序仿真没有输出！我应该从那分析啊！
我的源代码是：
/*It is a program of series input data to parallel out data,
which is used in 16DAPSK*/
`timescale 1us/1ns
module series_to_parallel(series_in,
convert_clk,
out_clk,
convert_rst,
parallel_out,
convert_out,
convert_begin,
busy);
input series_in;
input convert_clk;
input out_clk;
input convert_rst;
input convert_begin;
output[3:0] parallel_out;
output[3:0] convert_out;
output busy;
reg[3:0] parallel_out;
reg[3:0] convert_out;
reg busy;
reg [5:0] shift_state;
//reg convert_begin;
parameter shift_state_begin=6'b100000;
parameter shift_state_bit0=6'b000010;
parameter shift_state_bit1=6'b000100;
parameter shift_state_bit2=6'b001000;
parameter shift_state_bit3=6'b010000;
parameter shift_state_end= 6'b000001;
always @(posedge convert_rst or posedge convert_clk)
begin
if(convert_rst)
begin
//busy<=1'b1;
//convert_begin<=1'b1;
if(convert_begin)
begin
shift_state<=shift_state_begin;
parallel_out<=4'b0000;
end
else
begin
shift_state<=shift_state_end;
parallel_out<=4'b0000;
end
end
else
begin
case(shift_state)

shift_state_begin:
begin
if(convert_begin)
begin
shift_state<=shift_state_bit3;
busy<=1'b1;
end
else
begin
shift_state<=shift_state_end;
busy<=1'b0;
end
end
shift_state_bit3:
begin
if(convert_begin)
begin
parallel_out[3]<=series_in;
shift_state<=shift_state_bit2;
busy<=1'b1;
end
else
begin
shift_state<=shift_state_end;
busy<=1'b0;
end
end
shift_state_bit2:
begin
if(convert_begin)
begin
parallel_out[2]<=series_in;
shift_state<=shift_state_bit1;
busy<=1'b1;
end
else
begin
shift_state<=shift_state_end;
busy<=1'b0;
end
end
shift_state_bit1:
begin
if(convert_begin)
begin
parallel_out[1]<=series_in;
shift_state<=shift_state_bit0;
busy<=1'b1;
end
else
begin
shift_state<=shift_state_end;
busy<=1'b0;
end
end
shift_state_bit0:
begin
if(convert_begin)
begin
parallel_out[0]<=series_in;
shift_state<=shift_state_bit3;
busy<=1'b1;
end
else
begin
shift_state<=shift_state_end;
busy<=1'b0;
end
end
shift_state_end:
begin
if(convert_begin)
begin
shift_state<=shift_state_begin;
busy<=1'b1;
end
else
begin
shift_state<=shift_state_end;
busy<=1'b0;
end
end
default:
begin
shift_state<=shift_state_end;
//convert_begin<=1'b0;
end

endcase
end
//busy<=1'b0;
end
//?1/4?
always@(posedge[/email] out_clk or posedge convert_rst)
begin
if(convert_rst)
convert_out<=4'b0000;
else
convert_out<=parallel_out;
end
endmodule


请高人指点！

偶也是初学，不太懂，望高手解答

需要testbench吧

慢慢来，直接在ise里面起modelsim结果如何?
你编译FPGA厂商的库没有啊?

回复 #4 yangyuf 的帖子
我用的时Quartus，经过几番改正，终于出现输出结果了！正在打算编正余弦。还没找到头绪！

加油，继续努力

回复 #1 steelgirl 的帖子
编程风格不太好。
建议用这样的状态机"
always @(posedgeclk)
if
elsestate<=next_state;
always @(state or... )
...
case(state)
...
S_1:
S_2:
....
endcase