请yinchyang 等高手再解答我两个个问题，谢谢^_^
begin:count1s
reg[7:0] tempreg;
count=0;
tempreg=reg;
while(tempreg)//括号里的tempreg应该是个表达式的简写吧，表示的意思是什么?我觉得应该是tempreg！=8'b00000000,不知对不对^_^
begin
if(tempreg[0])
count=count+1;
tempreg=tempreg>>1;
end
end
2.在for循环初始化memory的例子中，
begin:init_mem
reg[7:0] tempi;
for(tempi=0;tempi<memsize;tempi=tempi+1)
memory[tempi]=0;//这里memory是个什么类型的变量?变量名[reg变量]这种格式不知道是什么意思?请指教，谢谢
end
tempreg=reg;
This line should be tempreg = rega; right?
The first question,
I think tempreg means tempreg ！= 8'h00; in fact, it means at least one bit is not zero.
The second question.
The variable array memory maybe defined like this,
reg [n:0] memory [m:0];
and n:0 defines the widhth of each element in the array,
and m:0 defines the amount of element in the array.
In the example, m should not less than 255.
Sorry again,
I can noly input with my poor english.
THANK YOU～～～
您能回答我 我已经“相当”高兴了 ^_^。
也就是说 while(tempreg！=0)可以简写为while(tempteg)吗?
memory[tempi]=0也就是对由8个寄存器组成的存储器组中的每个寄存器都置0是吧?
Yes,
But my suggestion is ,
while(tempreg！=8'h00),
Good coding style leads to health design.
But
Please do not call me "GaoShou" again, I am not an expert of Verilog.
THANK you。
我明白了谢谢你，您对我的帮助太大了不胜感激^_^
其实你可以看一下c语言 这和c语言是非常相像的 另外有一点while(tempreg) 其中的tempreg确切的说应该是非负的整数都为true,0肯定没问题,但是这个负整数有可能被有些软件就会编译为false
楼上的大侠，您说“tempreg确切的说应该是非负的整数都为true”，我觉得是不是应该是“所有非零的整数都为true”呢?因为只有当tempreg为true时，循环才会继续吧。而这个循环是为了计算寄存器中值为1的个数。还有一点，书上说reg型变量中的负数在运算时会当正数来使用，例如4位的二进制数开始赋值为－1，但当操作数时会当作＋15来用，是不是表示说计算机实际认为reg变量就是一个无符号数?谢谢
你的"非负整数都是true", 有问题吧? while(tempreg)应该是非零就循环吧?
自己顶～～～谁帮我解答下8楼的问题?
自己已经搞懂了。
hehe
In verilog, my suggestion is to treat veriable as signal vector,
although the syntax of verilog and C is almost the same, they express different things.
I think , inverilog
tempreg means at least one signal in the vector is not zero.
If we treat it as a integer, maybe we will get confusion.