我的这段VHDL程序有什么问题？帮我看看

我现在学习VHDL，写了一个程序包的小程序，但是编译总不通过，是按照书上的例子写的。
另外，程序包怎么样放到库里啊?我用的是Quartus II.多谢。
程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
PACKAGE am IS
FUNCTION fun(aa,bb:IN STD_LOGIC)RETURN STD_LOGIC;
END am;
PACKAGE BODY am IS
FUNCTION fun(aa,bb:IN STD_LOGIC)RETURN STD_LOGIC IS VARIABLE x:STD_LOGIC);
BEGIN
x:=aa and bb;
return x;
END fun;
END am;
ENTITY NewTest2 IS
PORT(a,b,c:IN STD_LOGIC;
j:IN STD_LOGIC_VECTOR(2 downto 0);
d,e:OUT STD_LOGIC;
f:OUT STD_LOGIC_VECTOR(2 downto 0));
END NewTest2;
ARCHITECTURE NewTest2_body of NewTest2 IS
BEGIN
d<=a and b and c;
PROCESS(j)
BEGIN
CASE j IS
WHEN "000"=>f<="000";
WHEN "001"=>f<="001";
WHEN "010"=>f<="010";
WHEN "011"=>f<="011";
WHEN "100"=>f<="100";
WHEN "101"=>f<="101";
WHEN "110"=>f<="110";
WHEN "111"=>f<="111";
END CASE;
e<=fun(a,b);
END PROCESS;
END NewTest2_body;
出错信息如下：
Error: VHDL syntax error at NewTest2.vhd(10) near text ")"; expecting ";"
Error: VHDL syntax error at NewTest2.vhd(19) near text "IN"; expecting a string literal or an identifier
Error: VHDL syntax error at NewTest2.vhd(21) near text "OUT"; expecting a string literal or an identifier
Error: VHDL error at NewTest2.vhd(43): name b cannot be used because it is already used for a previously declared item
Info: Found 0 design units, including 0 entities, in source file NewTest2.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings

我的这段VHDL程序有什么问题?帮我看看
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
library work;
use work.am.all
加上后面的程序包应该可以了