下面的warning是怎么产生的,不是很理解
input clk;
input rst;
input a;
output [7:0]b;
reg[7:0]temp;
reg [7:0]b;
reg [10:0]state;
reg[10:0]nextstate;
parameter idle=11'b00000000001,st0=11'b00000000010,st1=11'b00000000100,st2=11'b00000001000,st3=11'b00000010000,st4=11'b00000100000,st5=11'b00001000000,
st6=11'b00010000000,st7=11'b00100000000,st8=11'b01000000000,st9=11'b10000000000;
always @(negedge clk)
begin
if(rst)
begin
state<=idle;
temp<=8'b0;
b<=8'b1;
end
else
state<=nextstate;
end
always @(state)
begin
b=8'b1;
case(state)
idle:;
st0:begin
temp={temp,a};
b=8'b1;
end
st1:begin
temp={temp,a};
b=8'b1;
end
st2:begin
temp={temp,a};
b=8'b1;
end
st3:begin
temp={temp,a};
b=8'b1;
end
st4:begin
temp={temp,a};
b=8'b1;
end
st5:begin
temp={temp,a};
b=8'b1;
end
st6:begin
temp={temp,a};
b=8'b1;
end
st7:begin
temp={temp,a};
b=8'b1;
end
st8:b=temp;
st9:;
default:begin
temp=8'b0;
b=8'b1;
end
endcase
end
always @(state)
begin
case(state)
idle:nextstate=st0;
st0:nextstate=st1;
st1:nextstate=st2;
st2:nextstate=st3;
st3:nextstate=st4;
st4:nextstate=st5;
st5:nextstate=st6;
st6:nextstate=st7;
st7:nextstate=st8;
st8:nextstate=st9;
st9:nextstate=idle;
default:state=idle;
endcase
end
endmodule
下面的warning是怎么产生的,不是很理解
[这个贴子最后由sghxz在 2005/08/31 12:33pm 第 1 次编辑]
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at VCC
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Uniton signal > not replaced by logic
Signal is stuck at GND
写的是一组11串行数据进入,第一位无效,2-9有效,后面的无效,截取2-9位的数据