怎么回事！？
CLK180,
CLK270,
CLK2X,
CLK90,
CLKDV,
LOCKED,
CLKFB,
CLKIN,
RST
);
outputCLK0;
outputCLK180;
outputCLK270;
outputCLK2X;
outputCLK90;
outputCLKDV;
outputLOCKED;
outputCLKFB;
inputCLKIN;
inputRST;
defparam CLKDLL_inst.CLKDV_divIDE = 16.0;// Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
defparam CLKDLL_inst.DUTY_CYCLE_CORRECTION = "TRUE";// Duty cycle correction, TRUE or FALSE
defparam CLKDLL_inst.FACTORY_JF = 16'hC080;// FACTORY JF Values
defparam CLKDLL_inst.STARTUP_WAIT = "FALSE"; // Delay config DONE until DLL LOCK, TRUE/FALSE
CLKDLL CLKDLL_inst (
.CLK0(CLK0),// 0 degree DLL CLK ouptput
.CLK180(CLK180), // 180 degree DLL CLK output
.CLK270(CLK270), // 270 degree DLL CLK output
.CLK2X(CLK2X),// 2X DLL CLK output
.CLK90(CLK90),// 90 degree DLL CLK output
.CLKDV(CLKDV),// Divided DLL CLK out (CLKDV_divIDE)
.LOCKED(LOCKED), // DLL LOCK status output
.CLKFB(CLKFB),// DLL clock feedback
.CLKIN(CLKIN),// Clock input (from IBUFG, BUFG or DLL)
.RST(RST)// DLL asynchronous reset input
);
endmodule
综合会有以下错误：
ERROR:HDLCompilers:200 - DLL.v line 36 Target of defparam 'CLKDLL_inst.CLKDV_divIDE' does not exist
ERROR:HDLCompilers:200 - DLL.v line 37 Target of defparam 'CLKDLL_inst.DUTY_CYCLE_CORRECTION' does not exist
ERROR:HDLCompilers:200 - DLL.v line 38 Target of defparam 'CLKDLL_inst.FACTORY_JF' does not exist
ERROR:HDLCompilers:200 - DLL.v line 39 Target of defparam 'CLKDLL_inst.STARTUP_WAIT' does not exist
ERROR: XST failed
不知道咋整的每回都不能够用defparam?
谁碰到过拜托告诉我怎样解决呀?
怎么回事！?
放到例化后面呢
怎么回事！?
用XST综合时，你需要这样做：
DCM DCM_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND),
.PSCLK(GND),
.PSEN(GND),
.PSINCDEC(GND),
.RST(RST_IN),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(CLK90_BUF),
.CLK180(CLK180_BUF),
.CLK270(CLK270_BUF),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
// synthesis attribute CLKDV_divIDE of DCM_INST is "2.000000"
// synthesis attribute CLKFX_divIDE of DCM_INST is "1"
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is "4"
// synthesis attribute CLKIN_divIDE_BY_2 of DCM_INST is "FALSE"
// synthesis attribute CLKIN_PERIOD of DCM_INST is "10.000000"
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
// synthesis attribute FACTORY_JF of DCM_INST is "C080"
// synthesis attribute PHASE_SHIFT of DCM_INST is "0"
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
// synopsys translate_off
defparam DCM_INST.CLK_FEEDBACK = "1X";
defparam DCM_INST.CLKDV_divIDE = 2.000000;
defparam DCM_INST.CLKFX_divIDE = 1;
defparam DCM_INST.CLKFX_MULTIPLY = 4;
defparam DCM_INST.CLKIN_divIDE_BY_2 = "FALSE";
defparam DCM_INST.CLKIN_PERIOD = 10.000000;
defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_INST.FACTORY_JF = 16'hC080;
defparam DCM_INST.PHASE_SHIFT = 0;
defparam DCM_INST.STARTUP_WAIT = "FALSE";
// synopsys translate_on
你可以采用Xilinx的Architecture Wizard来产生实例。
怎么回事！?
我的Architecture Wizard没有SPARTAN II的只有III以上的！
放到后面也不行呀！
一样的错误。
怎么回事！?
我想语法都是一样的！可以照葫芦画瓢嘛！放到前面、后面无所谓。
怎么回事！?
叹息大侠都做了那么好的葫芦了，瓢也该画好了吧。
怎么回事！?
摆平了！下面是用ISE 调用synplify pro用modelsim仿真成功的程序,供有兴趣的新手参考.
module dll_standard
(
CLKIN,
RST,
CLK0,
CLK2X,
LOCKED,
CLKDV
);
defparam dll.CLKDV_divIDE = 16.0;
input CLKIN
//,RESET
;
output CLK0,
CLK2X,
LOCKED
,CLKDV
,RST
;
wire CLKIN_w,
RST,
CLK0_dll,
CLK2X_dll,
LOCKED_dll
,CLKDV_dll
;
IBUFG clkpad (
.I(CLKIN),
.O(CLKIN_w)
);
//IBUF rstpad (
//.I(RESET),
//.O(RESET_w)
//);
CLKDLL dll
(
.CLKIN(CLKIN_w),
.CLKFB(CLK0),
.RST(1'b0),
.CLK0(CLK0_dll),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(CLK2X_dll),
.CLKDV(CLKDV_dll),
.LOCKED(LOCKED_dll)
);
BUFG clkvg (
.I(CLKDV_dll),
.O(CLKDV)
);
BUFG clkg (
.I(CLK0_dll),
.O(CLK0)
);
BUFG clk2xg (
.I(CLK2X_dll),
.O(CLK2X)
);
OBUF lckpad (
.I(LOCKED_dll),
.O(LOCKED)
);
SRL16 SRL16_inst
(
.Q(LOCK),// SRL data output
.A0(1'b1),// Select[0] input
.A1(1'b1),// Select[1] input
.A2(1'b1),// Select[2] input
.A3(1'b1),// Select[3] input
.CLK(CLKDV_dll),// Clock input
.D(LOCKED_dll)// SRL data input
);
xor (RST,LOCKED_dll,LOCK);
endmodule
不过有一个问题:好象在那本资料上看见过不要用LOCK信号产生RESET信号,因为DLL 锁存之后，DLL LOCK 信号并不能保证随时都能插入LOCK 信号.
不知道我这样产生RST稳不稳定?
请高手开课！