望高手指点

我在设计中遇到问题，设计目的是将MASCLK分频得到CLK信号，同时置输出CLK为高时保持5个MASCLK时钟。程序如下，仿真时输出CLK不对，不知错在何处，望高手指点！谢谢！
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GENCLK IS
PORT(
MASCLK: INSTD_LOGIC;
K: INSTD_LOGIC_VECTOR(3 DOWNTO 0);
WDYCTL: OUTSTD_LOGIC_VECTOR(7 DOWNTO 0);
CLK,PK1,PK2,PK3,PK4: OUTSTD_LOGIC);
END GENCLK;
ARCHITECTURE a OF GENCLK IS
SIGNAL COUNT,CTL1,CTL2:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL QQ:STD_LOGIC;
BEGIN
PK1<=K(0);
PK2<=K(1);
PK3<=K(2);
PK4<=K(3);
CTL2<=CTL1+5;
WDYCTL<=CTL1;
PROCESS(MASCLK )
BEGIN
IF( MASCLK'EVENT AND MASCLK='1')THEN
IF (COUNT=CTL1)THEN
QQ<='1';
COUNT<=COUNT+1;
ELSIF(COUNT<CTL2 AND QQ='1')THEN
QQ<='1';
COUNT<=COUNT+1;
ELSIF(COUNT=CTL2 )THEN
COUNT<="00000000";
QQ<='0';
ELSE
COUNT<=COUNT+1;
QQ<='0';
END IF;
CLK<=QQ;
END IF;
END PROCESS;
PROCESS(K )
BEGIN
CASE K IS
WHEN"0001"=>CTL1<="00011110"; --P1.0 IS H, 6M
WHEN"0010"=>CTL1<="00010111"; --P1.1 IS H, 8M
--WHEN"0100"=>CTL1<="00010011"; --P3.4 IS H, 10M
WHEN OTHERS=>CTL1<="00100101";--WHEN P1.0 AND P1.1 AND P3.4 ARE ALL L, 4.5M
END CASE;
END PROCESS;
END a;

望高手指点
你的Vhdl用得不错，不过出了问题还是逐个信号向前追查比较好，毕竟不是语法方面的问题，还是自己动手好。