关于iic的一个问题
时间:10-02
整理:3721RD
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Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most
significant bit (MSB) first (see Fig.6). If a slave can’t
receive or transmit another complete byte of data until it
has performed some other function, for example servicing
an internal interrupt, it can hold the clock line SCL LOW to
force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data
and releases clock line SCL.
以上是iic规范里的一段话,请问如果用vhdl的话怎么实现这个功能,主设备怎么去得到scl上的信号,我是过将scl管脚定义为input,可是无法仿真,请高手指教,谢谢!
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most
significant bit (MSB) first (see Fig.6). If a slave can’t
receive or transmit another complete byte of data until it
has performed some other function, for example servicing
an internal interrupt, it can hold the clock line SCL LOW to
force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data
and releases clock line SCL.
以上是iic规范里的一段话,请问如果用vhdl的话怎么实现这个功能,主设备怎么去得到scl上的信号,我是过将scl管脚定义为input,可是无法仿真,请高手指教,谢谢!
关于iic的一个问题
SCL信号是主设备发出的
关于iic的一个问题
首先谢谢小编回复!
我的意思是当从设备忙时它会拉低scl,由于线与的原因scl会变为低,根据协议这是
主设备要进入等待状态,这样的话它就必须能够采样到scl上的电平,我现在采用的方法是使用两个模块,一个负责基本的iic收发,一个用来采样scl上的电平,当采样到一定时间的低电平后,通知收发模块进入等待状态,请问这样做会不会造成其他问题
,例如会不会对采样scl的那个管脚造成损坏,我记得在这里看过一篇文章说的是接到同一个输入管脚的两个管脚不要同时输出
关于iic的一个问题
对于3态输出脚,是没有影响的