请教高手:为什么这个锁相环电路总是锁不住?
(1)Please check the PCB layout of the loop-filter part.From you description, some kind of Spurs has modulated in the loop.
(2) Check Fin of the PLL IC whether you have applied enough voltage.
回复小编3
感谢!
现在发现问题在于PLL的 fout 输出 无论为fr 还是fp时,输出波形是脉冲 而不是方波!我也检查过 Vcc ,Vp,PS 以及Zs 的电压,都在datasheet上的 typ 范围附近。fr 和fp 的频率是对的,就是波形不对,这样使得比较后的电荷泵输出就有问题了,检查过晶振的输入Vpp也在datasheet的typ值,fin的输入耦合电容也从小到大调整过,问题可能出在哪里呢?劳驾有经验专家给点提示为谢!
濾波器輸出必須無波動的直流,否則輸出頻率是某範圍來回移動。
因此請看元件資料第20頁的被動式RC濾波器之中的電阻串聯電容
(R1=4.2K串C1=0.047uF),由於你的條件不同於資料條件,
需要變更設計。依照你的問題在此於C1值太小,可用C1=0.1~1uF
試驗;其次R1可以在略小些定R1=1K~4.2K。
回复yeutay
滤波器元件值是用锁相环软件计算出来的,根据如下参数得到:鉴相频率现在设为 1MHz, 电荷泵电流1.5 mA,Kvco=200 MHz/V,atten = 20dB,phase margin =45, loop bandwidth =15 kHz, 计算结果为(参照datasheet 第20页滤波器从左到右编号):C1 = 6.6nF, C2 = 37 nF, R2= 780, C3=305 pF, R3=1.56k. 用另外一个软件计算结果为:
C1 = 8.4 C2 = 61.2 R2= 600,C3=720, R3=2.2k. 两个计算结果 从Bode图上反映基本没有多大差异。
If you found output (current amplifer), it is correct.Maybe, you can increase the order of loop filter from 2nd to 3rd order.
reply to Rayengine
The question is that the output of the charge pump is NOT correct. Referring to the Datasheet pp. 14 of MB15E07SL, the waveform for both fr and fp should be square waves, but measurements found they are pulses. maybe, I think, the pulse waveform leads to the output of the charge pump being NOT correct. However, why the waveform for fr and fp are both pulses? It should be squarewaves!
Seems it is possible that the Ref clock or VCO feedback signal is not correct or not clean, please pay attention to the PLL layout and signal quality,I faced such situation when I had very low phase detector frequency the total phase noise was worse due to high prescaler number.
1、make sure the open loop is OK
2、the data to PLL IC is OK.such as:clkdatastb