Silvaco Atlas器件仿真问题
时间:03-15
整理:3721RD
点击:
我用atlas 做了一个VDMOS,但是在求解初始化的时候,总是出现,Warning: Internal error in linear solver.This situation rarely occurs in normal circumstances.
This error could indicate a ill-defined problem.
Check structure and models for possible conflicts.
Warning:Cannot trap. Cannot reduce bias
step.Choose smaller bias step size, or
check structure and or models.
这个是什么问题呢,是网格吗,我修改好几天了,都没有解决,求助啊
This error could indicate a ill-defined problem.
Check structure and models for possible conflicts.
Warning:Cannot trap. Cannot reduce bias
step.Choose smaller bias step size, or
check structure and or models.
这个是什么问题呢,是网格吗,我修改好几天了,都没有解决,求助啊
该网格
改网格也没有用啊,结构感觉也是对的,是不是模型添加的问题?
小编问题现在解决了吗