dc 遇到的坑
但是后面的读入文件时仍然会报错，无法找到相关的宏。在dc_shell中输入
read_file -help
Usage: read_file# read file from disk
[-autoread](enables autoread mode)
[-format format_name](default is db)
[-single_file file_name]
(group all designs into this file)
[-define macro_names](list of top-level macros, verilog and
SystemVerilog only)
[-library library_name]
(Use this library as the work library,
Vhdl only)
[-work library_name](Use this library as the work library,
VHDL only)
[-rtl](register transfer-level verilog/vhdl
format)
[-scenarios scenario_list]
(set of scenarios to be read from ddc file)
[-active_scenarios active_scenario_list]
(set of scenarios to be made active)
[-top top](name of the top design)
[-recursive](autoread recurses over subdirectories)
[-exclude exclude_list]
(files to be excluded from autoread)
[-rebuild](forced analyze of all autoread files)
[-verbose](autoread verbose output)
[-output_script output_script]
(autoread output script file name)
[-param param](autoread param for elaboration of top
design)
[file_list](list of files to read)
这里有一个-define 的选项，可以声明全局的宏，这样读入其他文件就不会报错了
例如：
read_file -format verilog -rtl -define {DLY=0.3 SYN_ON} {a.v b.v c.v ......}
-define {DLY=#0.3 SYN_ON} 声明了两个宏，DLY 对应#0.3， SYN_ON 声明了一个空的宏。
2， Information: Building the design 'sub' instantiated from design
'top' with the parameters
"xxxxxx". (HDL-193)
Warning: Cannot find the design 'sub' in the library 'WORK'. (LBR-1)
当顶层模块例化了带参数的子模块时，link 时找不到对应的子模块。
这是因为使用了read_file/read_verilog， 使用该命令等价于analyze xxx.v +elaborate,
read_file/read_verilog 会直接分析，并且编译。但是在编译top 时因为带有参数的sub_module 名字会发生变化。
就会报告Warning: Cannot find the design 'sub' in the library 'WORK'. (LBR-1)
此时应该使用analyze + elaborate 的方法：
analyze -format verilog {define.v top.v, sub.v}
elaborate top
这样就不会报找不到design的错了。
file mkdir ./work
define_design_lib WORK -path ./work
analyze 的用法
analyze -help
Usage: analyze# analyze hdl files
[-autoread](enables autoread mode)
[-vcs vcs_opts](an option string in VCS command-line
syntax)
[-library library_name]
(use this library as the work library)
[-uses design_libs](ordered list of design library identifiers)
[-work library_name](use this library as the work library)
[-format format_string]
(the format of the hdl file:
Values: Undefined, vhdl, verilog,
sverilog)
[-update](update analysis from original source)
[-create_update](create .update file for analyze -update)
[-define macro names](list of top-level macros, Verilog only)
[-top top](name of the top design)
[-recursive](autoread recurses over subdirectories)
[-exclude exclude_list]
(files to be excluded from autoread)
[-rebuild](forced analyze of all autoread files)
[-verbose](autoread verbose output)
[-output_script output_string]
(autoread output script file name)
[file_list](files to read in)
compile# compile design[-map_effort effort](map effort: low, medium, high)
[-area_effort effort](area effort: none, low, medium, high)
[-power_effort effort] (power effort: none, low, medium, high)
[-incremental_mapping] (perform only incremental mapping changes)
[-exact_map](sequential cells to be mapped exactly as indicated in HDL)
[-ungroup_all](ungroup all hierarchy)
[-boundary_optimization]
(optimize across hierarchical boundaries)
[-auto_ungroup automatically ungroup small hierarchies]
(auto ungroup: area, delay)
[-no_design_rule](don't fix design rules)
[-no_map](don't map design; leave as generic logic)
[-only_design_rule](only fix design rules)
[-only_hold_time](only fix hold time violations)
[-top](optimize the interface logic of the hierarchical sub-designs)
[-scan](replace all sequential elements by scan equivalent)
[-gate_clock](optimize clock gating)
compile# compile design
[-map_effort effort](map effort: low, medium, high)
[-area_effort effort](area effort: none, low, medium, high)
[-power_effort effort] (power effort: none, low, medium, high)
[-incremental_mapping] (perform only incremental mapping changes)
[-exact_map](sequential cells to be mapped exactly as indicated in HDL)
[-ungroup_all](ungroup all hierarchy)
[-boundary_optimization]
(optimize across hierarchical boundaries)
[-auto_ungroup automatically ungroup small hierarchies]
(auto ungroup: area, delay)
[-no_design_rule](don't fix design rules)
[-no_map](don't map design; leave as generic logic)
[-only_design_rule](only fix design rules)
[-only_hold_time](only fix hold time violations)
[-top](optimize the interface logic of the hierarchical sub-designs)
[-scan](replace all sequential elements by scan equivalent)
[-gate_clock](optimize clock gating)
分析到位。