someone can upload CadenceLow-PowerMethodologyKit8.2.0

someone can upload CadenceLow-PowerMethodologyKit8.2.0The Cadence Low-Power Methodology Kit 8.2.0 is an update release of the Cadence Low-Power
Methodology Kit 8.1.0. This Kit includes updates to following modules and tool versions as below:
1Kit Content Overview
2Digital Low Power Methodology
3Library Qualification
4SRD Overview
5Low Power RTL Design
6MSV and DVFS
7PSO
8CPF Creation, Authoring and Refining: Update
9Low Power Synthesis: Update
10Power Aware Design for Test: Update
11Conformal Low Power: Update
12Low-Power Functional and Formal Verification: Update
13LP ECO Methodology: Update
14Floorplanning for LP design and I/O ring Development: Update
15Power planning: Update
16LP timing and SI Closure: Update
17PV: Update
18Power Sign Off: Update
19VoltageStorm View generation: Update
20QRC techfile generation: Update
21ECSM generation: Update
22CDB view generation: Update
23CapTable Generation: Update
24Design Reuse: Update
Key Feature Updates
1.Tool BoM update for all the tools used (please refer to README for Tool Versions)
2.Work around were reduced as tools CCRs got fixed
3.CPF1.0e, Hierarchal CPF
4.Integrater for CPF merging
5.Physical Synthesis
6.Power Exploration based on build power model
7.Foundation Flow for PnR
8.CPF based timing and SI flow for top level
9.ELC for ECSM generation (SLC last time)
10. Multithreading for SoCE
11. verilog/SV based new verification environment for Verification
12.IEM for the low power mode and transition coverage
13. Flow improvement in Scan and Mbist

http://bbs.eetop.cn/viewthread.p ... 2BMethodology%2BKit

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Hmm... Hmm... Good information...But not enough credit...

must need very cell to download
why only 5mb is limit on eetop

must need very many cell to download
why only 5mb is limit on eetop

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http://bbs.eetop.cn/viewthread.p ... p;extra=&page=1

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Link for download?