最新Cadence SPB16.6 Hotfix S031下载
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726553FSPCAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
1257631 FSPDE-hdl_SCHEMATIC SchematicGeneration selects incorrect symbol version
1273456 ALLEGRO_EDITOR PLACEMENTPlace module instance causes Allegro tocrash
1277099 ALLEGRO_EDITOR INTERACTIVClines and pins are disconnected eventhough they are at the same x, y coordinate.
1280913 ALLEGRO_EDITOR EDIT_ETCHAdd Connect should be able to be madeby go strAIght even though the cursor is not exist on straight line
1282491 ADWPURGEADW PURGE is removing Page Name datain DEHDL
1283045 ALLEGRO_EDITOR DATABASEEcset not getting downreved.
1283138 SIP_layoutIC_IO_EDITINGsymed app mode chooses wrong text blocksizes for I/O driver inst names
1283227 PDN_ANALYSISPCB_STATICIRDROP Enhancement request to add32 bit files for IRdrop
1284656 CONCEPT_HDLCREFERCrefer fails on large design
1285814 CONCEPT_HDLCOREDEHDL crash on opening the Design
1285967 ALLEGRO_EDITOR EDIT_ETCHSlide via in circle pad ===================================================
下载地址：http://pan.baidu.com/s/1eQpamRo
下下来看看能不能用
DATE: 08-22-2014HOTFIX VERSION: 034
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932528CONCEPT_HDLOTHERAbility to handle reusemodule in soft reuse blocks.
1137838 FSPGUIAbility to add notes to the canvas
1274382 ALLEGRO_EDITOR OTHERRetaining rats at the end of the clines or vias
1283575 FSPDE-HDL_SCHEMATIC Force Schegen to use symbols from released library
1296331 CONCEPT_HDLCOMP_BROWSERCSV export no longer works properly from Component Browser
1297855 F2BDESIGNSYNCds -automode error
1298028 CONCEPT_HDLCREFERCreferHDL crashes
1299607 SIG_INTEGRITYOTHERAutoModel should generate ESpice models for illegal values
1299609 CONCEPT_HDLOTHERAutoModel should make an ESpice model for a 3 pin Capacitor
1302013 ALLEGRO_EDITOR EDIT_ETCHAiBT Crashes Allegro for nets having T points
1302209 SPIFOTHERCan't Export to Router and create a Specctra file.
1302242 F2BPACKAGERXLPackaging a hierarchical project does not create a full pstdmodeldat file
1302285 SCMCONN_SERVERDSCS-120: Failed to open file <filename.xcon> in write mode
1302310 ALLEGRO_EDITOR INTERFACESNeed way to have user defined license packages win over Cadence products.
1302638 F2BPACKAGERXLFunction swaps are not backannotated into the schematic
1303170 SIP_LAYOUTDIE_STACK_EDITOR Using Die Properties to move a die to the bottom side causes some entities to disacociate from the part
1303214 CONCEPT_HDLCOREDEHDL crashes
1303219 ALLEGRO_EDITOR COLORThe user preference variable color_dlg_auto_apply changes the colors in the Display category
1303685 CONCEPT_HDLCOREDEHDL crashes when I save page 3
1303897 CONCEPT_HDLCORETool crashes intermittently when editing top-level schematic
1304656 APDPLATING_BARAdd Plating Bar command convert the Clines having Arcs to 45 Degree segments
1306467 CONCEPT_HDLCOREConcepthdl crashes during model assignmnt
DATE: 08-7-2014HOTFIX VERSION: 033
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1265152 CONSTRAINT_MGR OTHERIn CM, for a new worksheet, the Actuals are not seen for Class-Class Objects.
1269155 CONSTRAINT_MGR INTERACTIVConstraint manager does not evaluate the formulas if the min value is more than the max value
1279589 APDNCDuplicated Drills
1280288 CONSTRAINT_MGR OTHERThe option "rename existing refdes" is hidden while doing File>import>logic
1285122 CONSTRAINT_MGR UI_FORMSAnalysis Settings does not appear in constraint Manager Sigrity SI
1291054 CONCEPT_HDLARCHIVERarchiver fails to create the cds.lib & cpm files when the -views switch is used in the command line
1291186 SIP_LAYOUTDXF_IFExport DXF is incorrectly exporting the top layer pins when they aren?t specified in the output.
1292595 CONSTRAINT_MGR SCHEM_FTBRevision number reset in dcf when running Import Physical
1293346 ALLEGRO_EDITOR GRAPHICSsmd symbols with Step model not correctly shown in 3D Viewer
1293579 ADWPCBCACHEERROR(SPCOCD-553): Connectivity Server Error: Failed to load component cell 'ti_template.ets600_pogp_143p:sym_1'
1293733 SIG_EXPLOREREXTRACTTOPSigXP extraction: Bad memory usage in logicalop Head！ message is output on Linux
1293911 ALLEGRO_EDITOR EDIT_ETCHUsing AiPT on this design causes an unrelated via to be deleted
1296433 CONCEPT_HDLCOREDEHDL crashes when saving hierarchy
1296735 ALLEGRO_EDITOR NCCustomer want to know why we change the description in SPB166, it causes CAM350 can`t import drill file.
1296743 APDDEGASSINGDegassing creates wrong voids for second and subsequent shapes when multiple shapes are selected
1296803 ALLEGRO_EDITOR OTHERCan no longer access some drawing subclasses in 16.6
1298421 ADWLRMArtesyn: LRM cannot update the part.
1299871 APDWIREBONDThe axlSetAllProfilesVisible return all "nill"
1300186 ALLEGRO_EDITOR DATABASEDeleted NetGroups in DEHDL appear in the Allegro PCB CM
1300961 CONSTRAINT_MGR CONCEPT_HDLcmdfeedback.exe crashes during import physical
1301180 ALLEGRO_EDITOR GRAPHICS3D Viewer for SMD footprint shows top pads on bottom layer and place bound wrongly
DATE: 07-25-2014HOTFIX VERSION: 032
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381127SPECCTRACROSSTALKSpecctra xtalk reports aren't correct
616770ALLEGRO_EDITOR COLORRemove the APPLY button in the Color Dialog window.
982944ALLEGRO_EDITOR COLORseperate the Etch to the Shape and the the Cline in the visibility window
982995ALLEGRO_EDITOR INTERACTIVShown infomation for the selected physical symbols
1024832 PSPICEPROBEShows wrong data & header when exporting trace to .txt
1063258 PSPICEAA_OPTcurve fit fails with errorsame data works in 16.5 Simulation error: out of range of data
1112360 PSPICEAA_OPTAdvacne analysis gives runtime error while using Optimizer in attached design
1154323 PCB_LIBRARIANVERIFICATIONCon2con is choosing incorrect Primitive from Chips file and failing FTB Checks
1184690 CONCEPT_HDLCOREWeird behavior of genview for split hierarchical blocks
1212577 PSPICEMODELEDITORIBIS translation fails without any information in log file
1213204 ALLEGRO_EDITOR PLACEMENTPlace Manually with existing fixed net behaving incorrectly
1213837 ALLEGRO_EDITOR INTERACTIVWhen copying a stacked via the temp highlight does not display on the last layer of the stack.
1216519 SPECCTRAROUTEAutorouter will not add BB via between uvia within the BGA area
1220655 PSPICEDEHDL_NETLISTERSupport for automatic addition for Power source and Ground Node for Globalsin DEHDL PSpice netlisting
1223018 CAPTUREOTHERDiff pair Auto Setup not working for the buses.
1225689 PSPICEAA_SMOKESmoke analysis crashes with attached testcase
1232124 CONCEPT_HDLCOMP_BROWSERunable to generate ppt_options.dat file in first go
1235059 PCB_LIBRARIANIMPORT_CSVpin_delays not being imported into PDV
1238815 CAPTUREOTHERCapture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
1239241 ALLEGRO_EDITOR INTERACTIVVia replacement doesn't replace with correct via but right padstack name.
1240201 ALLEGRO_EDITOR EDIT_ETCHRPD DRC unresolved evenif HUD turns Green
1240314 PSPICESIMULATORGetting internal error,overflow for the second run
1242805 ALLEGRO_EDITOR DRC_CONSTRno_drc_progress_meter variable hangs allegro after running update drc
1243267 ADWTDAURL to TDO-SharePoint should be defined in CPM File
1244857 ADWTDAPolicy File Variables not working correctly in policy file
1245779 CONCEPT_HDLCONSTRAINT_MGRObsolete objects in DEHDL CM
1246811 CISEXPLOREROption to keep the part type tree in CIS explorer expanded on every invoke
1246964 PSPICEPROBESimulation Crashes in 16.6 but running successfully in 16.5
1248782 CONCEPT_HDLCOREDisplay winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design
1249238 CONCEPT_HDLCOREUprev from 16.3 splatters text around sch page
1249692 ALLEGRO_EDITOR GRAPHICS3D Viewer is wrong when resizing its window.
1249850 ALLEGRO_EDITOR SHAPEWith shape_rki_autoclip Route Keepin to Shape DRC is created
1250683 ALLEGRO_EDITOR INTERACTIVdevpath corrupts if edited from user preferences.
1252059 ALLEGRO_EDITOR INTERACTIVPreference Editor is unable to delete a previous path entry for library paths
1253563 SIP_LAYOUTDEGASSINGNot getting degassing voids when close to shape in center of design
1254319 ALLEGRO_EDITOR GRAPHICSENH: Functionality to change the 3D Model color for more realistic view
1254562 ALLEGRO_EDITOR DATABASEUnable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
1255169 CONCEPT_HDLOTHERADW (BPc) Packager should report the specific corrupt directive in the .cpm file
1255573 ALLEGRO_EDITOR DRC_CONSTRNeed soldermask DRC checks when same net via and smd pad overlaps
1257950 CONSTRAINT_MGR SCHEM_FTBChanging xnet name on Allegro CM.
1258165 F2BDESIGNVARIchanging visibility of Probe_number in variant schematic changes it to $Porbe_number
1258274 PCB_LIBRARIANVERIFICATIONcon2con crash with no notification or error message
1258860 CAPTUREPROJECT_MANAGERBug: Text Editor (File> New> VHDL File) filters characters from Text
1258872 CONCEPT_HDLCOREObjects are copied (instead of moved) when moved from sheet to sheet
1259284 CONCEPT_HDLPDFHDL_POWER ( global) net does not get transferred to the published pdf
1259375 CONCEPT_HDLCOREHelp link to cdnUsers.org needs to be changed
1259860 ALLEGRO_EDITOR INTERACTIVEdit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
1260002 ALLEGRO_EDITOR INTERACTIVAlt sym hard is not obeyed when using Edit > Move > Mirror
1260006 ALLEGRO_EDITOR PLACEMENTfunckey r iange 90 rotation issue
1260667 ALLEGRO_EDITOR EDIT_ETCHAllegro crashes when running AICC command on few Diff Pair traces.
1260763 CONCEPT_HDLCOREExport Physical fails with $TEMP entry in Setup-Tools
1260847 SIP_LAYOUTSYMB_EDIT_APPMOD Border texts seen as triangles.
1260948 ALLEGRO_EDITOR SHAPEDynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
1262011 ALLEGRO_EDITOR PLACEMENTKey Properties on Component Instance/ Definition on available to use with Quickplace by Property
1262322 ALLEGRO_EDITOR PADS_INPads_in can not translate route keepout which specified for the all layers.
1262626 CONCEPT_HDLCOREPROBE NUMBER attributes lost from the nets after upreving the design
1263592 PCB_LIBRARIANVERIFICATIONUnable to check in Schematic Model due to pc.db file
1263685 ALLEGRO_EDITOR INTERACTIVEditing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
1263704 ALLEGRO_EDITOR EDIT_ETCHBug - AiTR wrongly deletes blind vias and do reroutes.
1265120 ALLEGRO_EDITOR SHAPERequire voids in dynamic shapes to use pad value
1265275 ALLEGRO_EDITOR DRC_TIMING_CHKWhen XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
1265633 PSPICESIMULATORBias point result is different in consecutive simulation run of the attached project
1266349 ALLEGRO_EDITOR PLACEMENTRotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
1267541 PSPICEPROBEpspice.exe does not exit when run from command line
1267707 ALLEGRO_EDITOR PLACEMENTMirror Command - preselect/postselect bug with general edit mode
1268299 PSPICESTABILITYPspice crash on attached design
1270879 ALLEGRO_EDITOR COLORColor view save creates .color file using older extension
1271295 SIP_LAYOUTDIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.
1271385 CONCEPT_HDLCORELocked property can still be added
1271853 APDOTHERWhen using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.
1272197 CONCEPT_HDLCOREconcepthdl_menu.txt contains invalid Variants menu
1272318 CAPTUREGEN_BOMBOM_IGNORE not working for Capture BOM on hierarchical designs.
1272743 ALLEGRO_EDITOR PADS_INPADS Library Translator does not open the Options dialog window.
1273517 F2BPACKAGERXLNetrev error - ERROR(40) Object not found in database
1274000 ALLEGRO_EDITOR DATABASEPCB layer can't be removed
1274530 ALLEGRO_EDITOR INTERACTIVAdd Circle radius value changes next time using this command
1274697 PSPICEAA_MCpspiceaa crashes when running Advanced analysis monte carlo for the attached design
1275154 CONCEPT_HDLCOREHierarchical Blocks lose ref designators when moved to another page
1275724 GRECOREAiDT delete another clines
1275831 ALLEGRO_EDITOR DRC_CONSTRWaived DRCs return when using multi-thread DRC check
1275834 CONCEPT_HDLCOREERROR (SPCOCD-569) on global bus
1276334 ALLEGRO_EDITOR PADS_INPADS Library Import problem with outlines
1277062 ALLEGRO_EDITOR PLACEMENTSwapping parts from top to bottom Orientation changes
1278746 ALLEGRO_EDITOR DRC_CONSTRPackage to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
1278804 CONCEPT_HDLCOPY_PROJECTCopy project crashes
1279362 ALLEGRO_EDITOR INTERACTIVUser SKILL file makes Allegro Icons gone away
1279619 ALLEGRO_EDITOR DRC_CONSTRNetgroup in a Netclass doesn't inherit Spacing Cset
1279815 CONCEPT_HDLCOREText > Change and RMB Editor does not allow multiple text edits
1279876 ALLEGRO_EDITOR DATABASEUsing the Curved option in Fillets results in a pad to shape DRC
1280435 F2BBOMBOMHDL with variant repeats the PART_NUMBER value
1281669 CONCEPT_HDLCOMP_BROWSERMatch Any radio button in Component Browser didn't work.
1282001 ALLEGRO_EDITOR DRC_CONSTRUpdating the DRCs on this design cause the DRC count to change on every update
1282480 SIP_LAYOUTWIREBONDInfo on the Wire Count property needs to be updated indicating that it is a User Defined Property
1283952 ALLEGRO_EDITOR PLOTTINGPublished pdf does not show dotted or phantom lines
1283957 ALLEGRO_EDITOR INTERACTIVReplace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6
1285588 ALLEGRO_EDITOR DRC_CONSTRDynamic phase control has wrong analysis result when add rectangle test bead in Clines.
1286743 ALLEGRO_EDITOR SHAPEGetting copper islands in the design after running the Delete Plating Bar command
1287215 ALLEGRO_VIEWER OTHERAllegro viewer plus does not support constraint regions
1288808 APDLOGICDerive Assignment stalls out or won?t finish and appears to run out of database room.
1289251 ALLEGRO_EDITOR SCHEM_FTBPin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
1289293 F2BDESIGNVARIWarning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present
1289809 SCMVERILOG_IMPORTUser not able to import a verilog netlist into SCM
1290696 CONCEPT_HDLCORECopying a net name repeatedly causes it to go off grid
1291162 CONCEPT_HDLCREFERcrefer crashes when selecting generate cross refernece for all nets selected
1291285 SIP_LAYOUTIMPORT_DATAReplacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
1291658 ALLEGRO_EDITOR INTERACTIVCannot add Frectangle to Group
1292180 ALLEGRO_EDITOR SKILLAllegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
1292210 CONCEPT_HDLCOREDEHDL crash if design was opened with -nonetlistuprev option.
1292278 SIP_LAYOUTWIREBONDWhen creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer
1292282 SIP_LAYOUTINTERACTIVEGetting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
1293381 SIP_LAYOUTIMPORT_DATAImport SPD2 error
1293889 CONCEPT_HDLPAGE_MGMTpage name regression result deleted by netassembler
1294124 ALLEGRO_EDITOR INTERACTIVSamsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
1294749 ALLEGRO_EDITOR ARTWORKNull pad is flagged as an error that break Thales automatic tape out
1294777 ALLEGRO_EDITOR SYMBOLMechanical symbols missed on STEP result
DATE: 08-22-2014HOTFIX VERSION: 034
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932528CONCEPT_HDLOTHERAbility to handle reusemodule in soft reuse blocks.
1137838 FSPGUIAbility to add notes to the canvas
1274382 ALLEGRO_EDITOR OTHERRetaining rats at the end of the clines or vias
1283575 FSPDE-HDL_SCHEMATIC Force Schegen to use symbols from released library
1296331 CONCEPT_HDLCOMP_BROWSERCSV export no longer works properly from Component Browser
1297855 F2BDESIGNSYNCds -automode error
1298028 CONCEPT_HDLCREFERCreferHDL crashes
1299607 SIG_INTEGRITYOTHERAutoModel should generate ESpice models for illegal values
1299609 CONCEPT_HDLOTHERAutoModel should make an ESpice model for a 3 pin Capacitor
1302013 ALLEGRO_EDITOR EDIT_ETCHAiBT Crashes Allegro for nets having T points
1302209 SPIFOTHERCan't Export to Router and create a Specctra file.
1302242 F2BPACKAGERXLPackaging a hierarchical project does not create a full pstdmodeldat file
1302285 SCMCONN_SERVERDSCS-120: Failed to open file <filename.xcon> in write mode
1302310 ALLEGRO_EDITOR INTERFACESNeed way to have user defined license packages win over Cadence products.
1302638 F2BPACKAGERXLFunction swaps are not backannotated into the schematic
1303170 SIP_LAYOUTDIE_STACK_EDITOR Using Die Properties to move a die to the bottom side causes some entities to disacociate from the part
1303214 CONCEPT_HDLCOREDEHDL crashes
1303219 ALLEGRO_EDITOR COLORThe user preference variable color_dlg_auto_apply changes the colors in the Display category
1303685 CONCEPT_HDLCOREDEHDL crashes when I save page 3
1303897 CONCEPT_HDLCORETool crashes intermittently when editing top-level schematic
1304656 APDPLATING_BARAdd Plating Bar command convert the Clines having Arcs to 45 Degree segments
1306467 CONCEPT_HDLCOREConcepthdl crashes during model assignmnt
DATE: 08-7-2014HOTFIX VERSION: 033
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1265152 CONSTRAINT_MGR OTHERIn CM, for a new worksheet, the Actuals are not seen for Class-Class Objects.
1269155 CONSTRAINT_MGR INTERACTIVConstraint manager does not evaluate the formulas if the min value is more than the max value
1279589 APDNCDuplicated Drills
1280288 CONSTRAINT_MGR OTHERThe option "rename existing refdes" is hidden while doing File>import>logic
1285122 CONSTRAINT_MGR UI_FORMSAnalysis Settings does not appear in constraint Manager Sigrity SI
1291054 CONCEPT_HDLARCHIVERarchiver fails to create the cds.lib & cpm files when the -views switch is used in the command line
1291186 SIP_LAYOUTDXF_IFExport DXF is incorrectly exporting the top layer pins when they aren?t specified in the output.
1292595 CONSTRAINT_MGR SCHEM_FTBRevision number reset in dcf when running Import Physical
1293346 ALLEGRO_EDITOR GRAPHICSsmd symbols with Step model not correctly shown in 3D Viewer
1293579 ADWPCBCACHEERROR(SPCOCD-553): Connectivity Server Error: Failed to load component cell 'ti_template.ets600_pogp_143p:sym_1'
1293733 SIG_EXPLOREREXTRACTTOPSigXP extraction: Bad memory usage in logicalop Head！ message is output on Linux
1293911 ALLEGRO_EDITOR EDIT_ETCHUsing AiPT on this design causes an unrelated via to be deleted
1296433 CONCEPT_HDLCOREDEHDL crashes when saving hierarchy
1296735 ALLEGRO_EDITOR NCCustomer want to know why we change the description in SPB166, it causes CAM350 can`t import drill file.
1296743 APDDEGASSINGDegassing creates wrong voids for second and subsequent shapes when multiple shapes are selected
1296803 ALLEGRO_EDITOR OTHERCan no longer access some drawing subclasses in 16.6
1298421 ADWLRMArtesyn: LRM cannot update the part.
1299871 APDWIREBONDThe axlSetAllProfilesVisible return all "nill"
1300186 ALLEGRO_EDITOR DATABASEDeleted NetGroups in DEHDL appear in the Allegro PCB CM
1300961 CONSTRAINT_MGR CONCEPT_HDLcmdfeedback.exe crashes during import physical
1301180 ALLEGRO_EDITOR GRAPHICS3D Viewer for SMD footprint shows top pads on bottom layer and place bound wrongly
DATE: 07-25-2014HOTFIX VERSION: 032
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381127SPECCTRACROSSTALKSpecctra xtalk reports aren't correct
616770ALLEGRO_EDITOR COLORRemove the APPLY button in the Color Dialog window.
982944ALLEGRO_EDITOR COLORseperate the Etch to the Shape and the the Cline in the visibility window
982995ALLEGRO_EDITOR INTERACTIVShown infomation for the selected physical symbols
1024832 PSPICEPROBEShows wrong data & header when exporting trace to .txt
1063258 PSPICEAA_OPTcurve fit fails with errorsame data works in 16.5 Simulation error: out of range of data
1112360 PSPICEAA_OPTAdvacne analysis gives runtime error while using Optimizer in attached design
1154323 PCB_LIBRARIANVERIFICATIONCon2con is choosing incorrect Primitive from Chips file and failing FTB Checks
1184690 CONCEPT_HDLCOREWeird behavior of genview for split hierarchical blocks
1212577 PSPICEMODELEDITORIBIS translation fails without any information in log file
1213204 ALLEGRO_EDITOR PLACEMENTPlace Manually with existing fixed net behaving incorrectly
1213837 ALLEGRO_EDITOR INTERACTIVWhen copying a stacked via the temp highlight does not display on the last layer of the stack.
1216519 SPECCTRAROUTEAutorouter will not add BB via between uvia within the BGA area
1220655 PSPICEDEHDL_NETLISTERSupport for automatic addition for Power source and Ground Node for Globalsin DEHDL PSpice netlisting
1223018 CAPTUREOTHERDiff pair Auto Setup not working for the buses.
1225689 PSPICEAA_SMOKESmoke analysis crashes with attached testcase
1232124 CONCEPT_HDLCOMP_BROWSERunable to generate ppt_options.dat file in first go
1235059 PCB_LIBRARIANIMPORT_CSVpin_delays not being imported into PDV
1238815 CAPTUREOTHERCapture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
1239241 ALLEGRO_EDITOR INTERACTIVVia replacement doesn't replace with correct via but right padstack name.
1240201 ALLEGRO_EDITOR EDIT_ETCHRPD DRC unresolved evenif HUD turns Green
1240314 PSPICESIMULATORGetting internal error,overflow for the second run
1242805 ALLEGRO_EDITOR DRC_CONSTRno_drc_progress_meter variable hangs allegro after running update drc
1243267 ADWTDAURL to TDO-SharePoint should be defined in CPM File
1244857 ADWTDAPolicy File Variables not working correctly in policy file
1245779 CONCEPT_HDLCONSTRAINT_MGRObsolete objects in DEHDL CM
1246811 CISEXPLOREROption to keep the part type tree in CIS explorer expanded on every invoke
1246964 PSPICEPROBESimulation Crashes in 16.6 but running successfully in 16.5
1248782 CONCEPT_HDLCOREDisplay winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design
1249238 CONCEPT_HDLCOREUprev from 16.3 splatters text around sch page
1249692 ALLEGRO_EDITOR GRAPHICS3D Viewer is wrong when resizing its window.
1249850 ALLEGRO_EDITOR SHAPEWith shape_rki_autoclip Route Keepin to Shape DRC is created
1250683 ALLEGRO_EDITOR INTERACTIVdevpath corrupts if edited from user preferences.
1252059 ALLEGRO_EDITOR INTERACTIVPreference Editor is unable to delete a previous path entry for library paths
1253563 SIP_LAYOUTDEGASSINGNot getting degassing voids when close to shape in center of design
1254319 ALLEGRO_EDITOR GRAPHICSENH: Functionality to change the 3D Model color for more realistic view
1254562 ALLEGRO_EDITOR DATABASEUnable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
1255169 CONCEPT_HDLOTHERADW (BPc) Packager should report the specific corrupt directive in the .cpm file
1255573 ALLEGRO_EDITOR DRC_CONSTRNeed soldermask DRC checks when same net via and smd pad overlaps
1257950 CONSTRAINT_MGR SCHEM_FTBChanging xnet name on Allegro CM.
1258165 F2BDESIGNVARIchanging visibility of Probe_number in variant schematic changes it to $Porbe_number
1258274 PCB_LIBRARIANVERIFICATIONcon2con crash with no notification or error message
1258860 CAPTUREPROJECT_MANAGERBug: Text Editor (File> New> VHDL File) filters characters from Text
1258872 CONCEPT_HDLCOREObjects are copied (instead of moved) when moved from sheet to sheet
1259284 CONCEPT_HDLPDFHDL_POWER ( global) net does not get transferred to the published pdf
1259375 CONCEPT_HDLCOREHelp link to cdnUsers.org needs to be changed
1259860 ALLEGRO_EDITOR INTERACTIVEdit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
1260002 ALLEGRO_EDITOR INTERACTIVAlt sym hard is not obeyed when using Edit > Move > Mirror
1260006 ALLEGRO_EDITOR PLACEMENTfunckey r iange 90 rotation issue
1260667 ALLEGRO_EDITOR EDIT_ETCHAllegro crashes when running AICC command on few Diff Pair traces.
1260763 CONCEPT_HDLCOREExport Physical fails with $TEMP entry in Setup-Tools
1260847 SIP_LAYOUTSYMB_EDIT_APPMOD Border texts seen as triangles.
1260948 ALLEGRO_EDITOR SHAPEDynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
1262011 ALLEGRO_EDITOR PLACEMENTKey Properties on Component Instance/ Definition on available to use with Quickplace by Property
1262322 ALLEGRO_EDITOR PADS_INPads_in can not translate route keepout which specified for the all layers.
1262626 CONCEPT_HDLCOREPROBE NUMBER attributes lost from the nets after upreving the design
1263592 PCB_LIBRARIANVERIFICATIONUnable to check in Schematic Model due to pc.db file
1263685 ALLEGRO_EDITOR INTERACTIVEditing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
1263704 ALLEGRO_EDITOR EDIT_ETCHBug - AiTR wrongly deletes blind vias and do reroutes.
1265120 ALLEGRO_EDITOR SHAPERequire voids in dynamic shapes to use pad value
1265275 ALLEGRO_EDITOR DRC_TIMING_CHKWhen XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
1265633 PSPICESIMULATORBias point result is different in consecutive simulation run of the attached project
1266349 ALLEGRO_EDITOR PLACEMENTRotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
1267541 PSPICEPROBEpspice.exe does not exit when run from command line
1267707 ALLEGRO_EDITOR PLACEMENTMirror Command - preselect/postselect bug with general edit mode
1268299 PSPICESTABILITYPspice crash on attached design
1270879 ALLEGRO_EDITOR COLORColor view save creates .color file using older extension
1271295 SIP_LAYOUTDIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.
1271385 CONCEPT_HDLCORELocked property can still be added
1271853 APDOTHERWhen using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.
1272197 CONCEPT_HDLCOREconcepthdl_menu.txt contains invalid Variants menu
1272318 CAPTUREGEN_BOMBOM_IGNORE not working for Capture BOM on hierarchical designs.
1272743 ALLEGRO_EDITOR PADS_INPADS Library Translator does not open the Options dialog window.
1273517 F2BPACKAGERXLNetrev error - ERROR(40) Object not found in database
1274000 ALLEGRO_EDITOR DATABASEPCB layer can't be removed
1274530 ALLEGRO_EDITOR INTERACTIVAdd Circle radius value changes next time using this command
1274697 PSPICEAA_MCpspiceaa crashes when running Advanced analysis monte carlo for the attached design
1275154 CONCEPT_HDLCOREHierarchical Blocks lose ref designators when moved to another page
1275724 GRECOREAiDT delete another clines
1275831 ALLEGRO_EDITOR DRC_CONSTRWaived DRCs return when using multi-thread DRC check
1275834 CONCEPT_HDLCOREERROR (SPCOCD-569) on global bus
1276334 ALLEGRO_EDITOR PADS_INPADS Library Import problem with outlines
1277062 ALLEGRO_EDITOR PLACEMENTSwapping parts from top to bottom Orientation changes
1278746 ALLEGRO_EDITOR DRC_CONSTRPackage to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
1278804 CONCEPT_HDLCOPY_PROJECTCopy project crashes
1279362 ALLEGRO_EDITOR INTERACTIVUser SKILL file makes Allegro Icons gone away
1279619 ALLEGRO_EDITOR DRC_CONSTRNetgroup in a Netclass doesn't inherit Spacing Cset
1279815 CONCEPT_HDLCOREText > Change and RMB Editor does not allow multiple text edits
1279876 ALLEGRO_EDITOR DATABASEUsing the Curved option in Fillets results in a pad to shape DRC
1280435 F2BBOMBOMHDL with variant repeats the PART_NUMBER value
1281669 CONCEPT_HDLCOMP_BROWSERMatch Any radio button in Component Browser didn't work.
1282001 ALLEGRO_EDITOR DRC_CONSTRUpdating the DRCs on this design cause the DRC count to change on every update
1282480 SIP_LAYOUTWIREBONDInfo on the Wire Count property needs to be updated indicating that it is a User Defined Property
1283952 ALLEGRO_EDITOR PLOTTINGPublished pdf does not show dotted or phantom lines
1283957 ALLEGRO_EDITOR INTERACTIVReplace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6
1285588 ALLEGRO_EDITOR DRC_CONSTRDynamic phase control has wrong analysis result when add rectangle test bead in Clines.
1286743 ALLEGRO_EDITOR SHAPEGetting copper islands in the design after running the Delete Plating Bar command
1287215 ALLEGRO_VIEWER OTHERAllegro viewer plus does not support constraint regions
1288808 APDLOGICDerive Assignment stalls out or won?t finish and appears to run out of database room.
1289251 ALLEGRO_EDITOR SCHEM_FTBPin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
1289293 F2BDESIGNVARIWarning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present
1289809 SCMVERILOG_IMPORTUser not able to import a verilog netlist into SCM
1290696 CONCEPT_HDLCORECopying a net name repeatedly causes it to go off grid
1291162 CONCEPT_HDLCREFERcrefer crashes when selecting generate cross refernece for all nets selected
1291285 SIP_LAYOUTIMPORT_DATAReplacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
1291658 ALLEGRO_EDITOR INTERACTIVCannot add Frectangle to Group
1292180 ALLEGRO_EDITOR SKILLAllegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
1292210 CONCEPT_HDLCOREDEHDL crash if design was opened with -nonetlistuprev option.
1292278 SIP_LAYOUTWIREBONDWhen creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer
1292282 SIP_LAYOUTINTERACTIVEGetting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
1293381 SIP_LAYOUTIMPORT_DATAImport SPD2 error
1293889 CONCEPT_HDLPAGE_MGMTpage name regression result deleted by netassembler
1294124 ALLEGRO_EDITOR INTERACTIVSamsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
1294749 ALLEGRO_EDITOR ARTWORKNull pad is flagged as an error that break Thales automatic tape out
1294777 ALLEGRO_EDITOR SYMBOLMechanical symbols missed on STEP result
DATE: 08-22-2014HOTFIX VERSION: 034
===================================================================================================================================
CCRIDPRODUCTPRODUCTLEVEL2TITLE
===================================================================================================================================
932528CONCEPT_HDLOTHERAbility to handle reusemodule in soft reuse blocks.
1137838 FSPGUIAbility to add notes to the canvas
1274382 ALLEGRO_EDITOR OTHERRetaining rats at the end of the clines or vias
1283575 FSPDE-HDL_SCHEMATIC Force Schegen to use symbols from released library
1296331 CONCEPT_HDLCOMP_BROWSERCSV export no longer works properly from Component Browser
1297855 F2BDESIGNSYNCds -automode error
1298028 CONCEPT_HDLCREFERCreferHDL crashes
1299607 SIG_INTEGRITYOTHERAutoModel should generate ESpice models for illegal values
1299609 CONCEPT_HDLOTHERAutoModel should make an ESpice model for a 3 pin Capacitor
1302013 ALLEGRO_EDITOR EDIT_ETCHAiBT Crashes Allegro for nets having T points
1302209 SPIFOTHERCan't Export to Router and create a Specctra file.
1302242 F2BPACKAGERXLPackaging a hierarchical project does not create a full pstdmodeldat file
1302285 SCMCONN_SERVERDSCS-120: Failed to open file <filename.xcon> in write mode
1302310 ALLEGRO_EDITOR INTERFACESNeed way to have user defined license packages win over Cadence products.
1302638 F2BPACKAGERXLFunction swaps are not backannotated into the schematic
1303170 SIP_LAYOUTDIE_STACK_EDITOR Using Die Properties to move a die to the bottom side causes some entities to disacociate from the part
1303214 CONCEPT_HDLCOREDEHDL crashes
1303219 ALLEGRO_EDITOR COLORThe user preference variable color_dlg_auto_apply changes the colors in the Display category
1303685 CONCEPT_HDLCOREDEHDL crashes when I save page 3
1303897 CONCEPT_HDLCORETool crashes intermittently when editing top-level schematic
1304656 APDPLATING_BARAdd Plating Bar command convert the Clines having Arcs to 45 Degree segments
1306467 CONCEPT_HDLCOREConcepthdl crashes during model assignmnt
DATE: 08-22-2014HOTFIX VERSION: 034
已经到Hotfix 33了
试试看看
多谢了！
谢谢分享。