synplify ready ip core and other

examples encryted ip i find that on net
http://read.pudn.com/downloads152/sourcecode/embed/668240/CAST_jpeg_d-xact/JPEG_D/openip/hdl/verilog/jpeg_d/jpeg_d_core.v__.htm
see attach whats inside
so send me encrypted any 3rd party ip for decryption

1. `include "jpeg_d_package.v"
   
2. 
   
3. module jpeg_d_core (clk, hd_clk_en, en, rst, clr, mp_out_common_cbus, mp_out_d_cbus, mp_in_d_cbus, pixout_rdy, pixout, pixout_wen, pixout_eob, pixout_lbs, pixout_sob, scanactive, soi_eoi, eos, streamdin, streamfifodatavalid, streamren, ps_fifo_in_cbus, ps_fifo_out_cbus, dht_raddr, dht_dout, idct_in_cbus, idct_out_cbus, idctbuffer_dout, idctbuffer_out_cbus, qt_dout, qtables_out_cbus);
   
4. 
   
5. input clk;// Global clock
   
6. input hd_clk_en;// Global clock enable
   
7. input en;// Enable
   
8. input rst;// Asynchronous reset
   
9. input clr;// Synchronous clear
   
10. input[82:0] mp_out_common_cbus;// Data/control bus from markers' parser (common to encode and decode)
    
11. input[42:0] mp_out_d_cbus;// Data/control bus from markers' parser (only for decoder)
    
12. output[3:0] mp_in_d_cbus;// Data/control bus to markers' parser from decoder
    
13. wire[3:0] mp_in_d_cbus;
    
14. input pixout_rdy;// Ready to accept pixel data
    
15. output[7:0] pixout;// Pixel out data
    
16. wire[7:0] pixout;
    
17. output pixout_wen;// Pixel out data write enable
    
18. wire pixout_wen;
    
19. output pixout_eob;// End of block flag. Masks last sample of each block
    
20. wire pixout_eob;
    
21. output pixout_lbs;// Last block in scan flag. Masks last block's samples
    
22. wire pixout_lbs;
    
23. output pixout_sob;// Start of block flag. Masks first sample of each block.
    
24. wire pixout_sob;
    
25. output scanactive;// Scan-active flag (asserted when the decoder processes ecs data)
    
26. wire scanactive;
    
27. output[1:0] soi_eoi;// SOI-EOI flags. Asserted when the corresponding marker has been detected.
    
28. wire[1:0] soi_eoi;
    
29. output eos;// End Of Scan indicator
    
30. wire eos;
    
31. input[7:0] streamdin;// Data from stream fifo
    
32. input streamfifodatavalid;// Data valid flag for data coming from stream fifo
    
33. output streamren;// Stream fifo read enable
    
34. wire streamren;
    
35. input[33:0] ps_fifo_in_cbus;// Control/data bus from Huffman decoder's ouptut fifo
    
36. output[35:0] ps_fifo_out_cbus;// Control/data bus to Huffman decoder's ouptut fifo
    
37. wire[35:0] ps_fifo_out_cbus;
    
38. output[8:0] dht_raddr;// Huffman tables read address
    
39. wire[8:0] dht_raddr;
    
40. input[7:0] dht_dout;// Huffman tables read data
    
41. input[10:0] idct_in_cbus;// Data/control bus from IDCT
    
42. output[12:0] idct_out_cbus;// Data/control bus to IDCT
    
43. wire[12:0] idct_out_cbus;
    
44. input[10:0] idctbuffer_dout;// Data bus from IDCT buffer
    
45. output[29:0] idctbuffer_out_cbus;// Control/data bus to IDCT buffer
    
46. wire[29:0] idctbuffer_out_cbus;
    
47. input[7:0] qt_dout;// Q-tables data
    
48. output[18:0] qtables_out_cbus;// Control data bus to Q-tables
    
49. wire[18:0] qtables_out_cbus;
    
50. 
    
51. // Internal signal declarations
    
52. wire en1;// Global enable (1)
    
53. 
    
54. // Input fifo IF
    
55. wire[3:0] din_fifo_cbus;// Input fifo control bus
    
56. wire din_fifo_clr_1x;// Clear input fifo (slow clock domAIn/output)
    
57. wire din_fifo_empty;// Input fifo empty flag
    
58. wire din_fifo_full;// Input fifo full
    
59. wire din_fifo_ren;// Input fifo read enable
    
60. wire inwait_int;// Input wait (prevents reading from stream fifo)
    
61. 
    
62. // Q-Tables IF
    
63. wire[9:0] dqt_cbus;// Q-tables control bus
    
64. wire[1:0] tqi;// Q-Tables selector
    
65. wire e_d;// Enhanced quantization scheme selector
    
66. 
    
67. // Auxiliary Control/Status signals
    
68. wire ecs;// Entropy-coded scan processing flag (registered ecs_cu)
    
69. wire ecs_cu;// Entropy-coded scan processing flag
    
70. 
    
71. // MCU unit IF
    
72. wire[3:0] frame_himax;// Maximum horizontal subsampling factor
    
73. wire[3:0] frame_vimax;// Maximum vertical subsampling factor
    
74. wire[3:0] hi_fast;// Horizontal subsampling factor (fast)
    
75. wire[3:0] vi_fast;// Vertical subsampling factor (fast)
    
76. wire[3:0] hi_slow;// Horizontal subsampling factor (slow)
    
77. wire[3:0] vi_slow;// Vertical subsampling factor (slow)
    
78. wire[13:0] hmcu;// Horizontal MCU index
    
79. wire[13:0] vmcu;// Vertical MCU index
    
80. wire[1:0] mcu_cbus;// MCU unit control bus
    
81. wire[1:0] mcu_csj;// MCU's scan-component selector
    
82. wire sen;// Enable for latch parameters
    
83. wire[2:0] nf;// Number of components in frame
    
84. wire[15:0] x;// Number of samples in line
    
85. wire[15:0] y;// Number of lines
    
86. wire[15:0] ri;// Restart interval length
    
87. wire[2:0] ns;// Number of components in scan
    
88. 
    
89. // Huffman tables fifo IF
    
90. wire[1:0] htfifo_cbus;// Huffman Tables fifo control bus
    
91. wire[6:0] ht_cbus;// Huffman decoder's control bus
    
92. wire ht_fifo_clr;// Huffman Tables fifo clear
    
93. wire ht_fifo_empty;// Huffman tables fifo empty
    
94. wire ht_fifo_full;// Huffman tables fifo full
    
95. wire ht_fifo_ren;// Huffman Tables fifo read enable
    
96. wire huffd_datavalid;// Huffman decoder output valid
    
97. wire[7:0] tdin;// Huffman tables fifo ouptut data
    
98. 
    
99. // Huffman decoder IF
    
100. wire[31:0] huffd_din;// Huffman decoder input
     
101. wire[31:0] ecs_data;// Entropy-coded segment data
     
102. wire huffd_en;// Enable MCU unit
     
103. wire huffd_eob;// End of block flag from Huffman decoder
     
104. wire huffd_load;// Load from input fifo (drived from Huffman decoder)
     
105. wire huffd_lum_cr;// Luminance Chrominance selector
     
106. wire huffd_res;// Huffman decoder restrat flag
     
107. wire huffdclr;// Clear MCU unit
     
108. wire taj;// AC tables selector
     
109. 
     
110. // IDCT IF
     
111. wire idct_finished;// IDCT finshed flag
     
112. wire[1:0] idctcu_cbus;// IDCT control unit control bus
     
113. 
     
114. // Register file IF
     
115. wire[6:0] sof0_cbus;// SOF0 register control bus
     
116. wire[7:0] sof0ci;// Component identifier from from SOF0 marker
     
117. wire[4:0] sos_cbus;// SOS register control bus
     
118. 
     
119. // Implicit buffer signal declarations
     
120. wire eos_internal;
     
121. 
     
122. //-----------------------------------------------------------------------------
     
123. assign streamren = ~inwait_int;
     
124. //-----------------------------------------------------------------------------
     
125. // Assignments to/from control and busses data of markers parse
     
126. //-----------------------------------------------------------------------------
     
127. assign sof0ci= mp_out_common_cbus[82:75];
     
128. assign frame_himax = mp_out_common_cbus[3:0];
     
129. assign frame_vimax = mp_out_common_cbus[7:4];
     
130. assign ri= mp_out_common_cbus[23:8];
     
131. //-----------------------------------------------------------------------------
     
132. assign sof0_cbus= mp_out_d_cbus[6:0];
     
133. assign sos_cbus= mp_out_d_cbus[23:19];
     
134. assign dqt_cbus= mp_out_d_cbus[16:7];
     
135. assign htfifo_cbus[1]= mp_out_d_cbus[18] & en;
     
136. assign htfifo_cbus[0]= mp_out_d_cbus[17];
     
137. assign idctcu_cbus[1]= mp_out_d_cbus[27] & en;
     
138. assign idctcu_cbus[0]= mp_out_d_cbus[26] & en;
     
139. assign din_fifo_cbus[3] = mp_out_d_cbus[31] & en;
     
140. assign din_fifo_cbus[2] = mp_out_d_cbus[30] & en;
     
141. assign din_fifo_cbus[1] = mp_out_d_cbus[29] & en;
     
142. assign din_fifo_cbus[0] = mp_out_d_cbus[28] & en;
     
143. assign mcu_cbus[1]= mp_out_d_cbus[25] & en;
     
144. assign mcu_cbus[0]= mp_out_d_cbus[24] & en;
     
145. assign inwait_int= mp_out_d_cbus[42];
     
146. assign e_d= mp_out_d_cbus[38];
     
147. assign ecs_cu= mp_out_d_cbus[37];
     
148. assign sen= mp_out_d_cbus[39] & en;
     
149. assign soi_eoi= mp_out_d_cbus[41:40];
     
150. //-----------------------------------------------------------------------------
     
151. assign mp_in_d_cbus[0] = idct_finished;
     
152. assign mp_in_d_cbus[1] = ht_fifo_empty;
     
153. assign mp_in_d_cbus[2] = ht_fifo_full;
     
154. assign mp_in_d_cbus[3] = din_fifo_full;
     
155. //-----------------------------------------------------------------------------
     
156. assign en1 = en & hd_clk_en;
     
157. //-----------------------------------------------------------------------------
     
158. // Assert input fifo read enable, when global enable is asserted, huffman decoder is enabled,
     
159. // and huffman decoder asks for a new data
     
160. assign din_fifo_ren = huffd_en & huffd_load & en;
     
161. // Input to huffman decoder is either ecs-data (during decoding mode)
     
162. // or table specification data (during tables-programming mode)
     
163. assign huffd_din = (ecs == 1) ? ecs_data : {ecs_data[31:8], tdin};
     
164. // Clear read register of input fifo, whenever huffman decoder is cleared
     
165. assign din_fifo_clr_1x = (huffdclr | htfifo_cbus[0]) & en;
     
166. 
     
167. // Instance port mappings.
     
168. din_fifo u_din_fifo (
     
169. .clk(clk),
     
170. .hd_clk_en(hd_clk_en),
     
171. .clrx1(din_fifo_clr_1x),
     
172. .clrx4(din_fifo_cbus[1]),
     
173. .din(streamdin),
     
174. .en(en),
     
175. .flush(din_fifo_cbus[3]),
     
176. .ren(din_fifo_ren),
     
177. .rst(rst),
     
178. .wen(din_fifo_cbus[2]),
     
179. .dout(ecs_data),
     
180. .empty(din_fifo_empty),
     
181. .full(din_fifo_full)
     
182. );
     
183. 
     
184. ecs_data_processor u_ecs_data_processor (
     
185. .clk(clk),
     
186. .hd_clk_en(hd_clk_en),
     
187. .en(en),
     
188. .rst(rst),
     
189. .clr(clr),
     
190. .csj(mcu_csj),
     
191. .din_fifo_empty(din_fifo_empty),
     
192. .ecs(ecs),
     
193. .eos(eos_internal),
     
194. .ps_fifo_in_cbus(ps_fifo_in_cbus),
     
195. .dht_raddr(dht_raddr),
     
196. .dht_dout(dht_dout),
     
197. .ps_fifo_out_cbus(ps_fifo_out_cbus),
     
198. .huffd_run_program(ht_cbus[6]),
     
199. .huffd_cu_en(mcu_cbus[1]),
     
200. .huffd_res(huffd_res),
     
201. .huffd_din(huffd_din),
     
202. .huffd_cu_clr(mcu_cbus[0]),
     
203. .huffd_lum_cr(huffd_lum_cr),
     
204. .huffd_code_symbol(ht_cbus[5]),
     
205. .huffd_en_w(ht_cbus[1]),
     
206. .huffd_clr_w(ht_cbus[0]),
     
207. .huffd_use_ac_dc(ht_cbus[3]),
     
208. .huffd_ac_dc(ht_cbus[4]),
     
209. .huffdclr(huffdclr),
     
210. .huffd_eob(huffd_eob),
     
211. .huffd_load(huffd_load),
     
212. .huffd_datavalid(huffd_datavalid),
     
213. .huffden_r(huffd_en),
     
214. .idct_buffdout(idctbuffer_dout),
     
215. .idctbuffer_out_cbus(idctbuffer_out_cbus),
     
216. .idct_in_cbus(idct_in_cbus),
     
217. .idct_cu_clr(idctcu_cbus[0]),
     
218. .idct_cu_en(idctcu_cbus[1]),
     
219. .idct_finished(idct_finished),
     
220. .idct_out_cbus(idct_out_cbus),
     
221. .qt_din(streamdin),
     
222. .qt_dout(qt_dout),
     
223. .qt_en_w(dqt_cbus[0]),
     
224. .qt_tq_w(dqt_cbus[9:8]),
     
225. .qt_wen(dqt_cbus[1]),
     
226. .tqi(tqi),
     
227. .ns(ns),
     
228. .e_d(e_d),
     
229. .qt_addr_w(dqt_cbus[7:2]),
     
230. .qtables_out_cbus(qtables_out_cbus),
     
231. .pixout_rdy(pixout_rdy),
     
232. .pixout(pixout),
     
233. .pixout_eob(pixout_eob),
     
234. .pixout_lbs(pixout_lbs),
     
235. .pixout_sob(pixout_sob),
     
236. .pixout_wen(pixout_wen)
     
237. );
     
238. 
     
239. ht_fifo u_ht_fifo (
     
240. .clk(clk),
     
241. .hd_clk_en(hd_clk_en),
     
242. .clrx1(htfifo_cbus[0]),
     
243. .clrx4(htfifo_cbus[0]),
     
244. .din(streamdin),
     
245. .en(en),
     
246. .ren(ht_fifo_ren),
     
247. .rst(rst),
     
248. .wen(htfifo_cbus[1]),
     
249. .dout(tdin),
     
250. .empty(ht_fifo_empty),
     
251. .full(ht_fifo_full)
     
252. );
     
253. 
     
254. huffman_d_tables_cu u_huffman_d_tables_cu (
     
255. .clk(clk),
     
256. .clr(htfifo_cbus[0]),
     
257. .din(tdin),
     
258. .en(en),
     
259. .hd_clk_en(hd_clk_en),
     
260. .ht_fifo_empty(ht_fifo_empty),
     
261. .ht_fifo_full(ht_fifo_full),
     
262. .rst(rst),
     
263. .ht_cbus(ht_cbus),
     
264. .ht_fifo_clr(ht_fifo_clr),
     
265. .ht_fifo_ren(ht_fifo_ren)
     
266. );
     
267. 
     
268. jdreg_1 ecsdreg (
     
269. .clk(clk),
     
270. .d(ecs_cu),
     
271. .en(en1),
     
272. .rst(rst),
     
273. .q(ecs)
     
274. );
     
275. 
     
276. jdreg_1 scanactivereg (
     
277. .clk(clk),
     
278. .d(ecs_cu),
     
279. .en(en),
     
280. .rst(rst),
     
281. .q(scanactive)
     
282. );
     
283. 
     
284. mcuunit u_mcuunit (
     
285. .clk(clk),
     
286. .clrx1(huffdclr),
     
287. .clrx4(mcu_cbus[0]),
     
288. .en(huffd_en),
     
289. .frame_himax(frame_himax),
     
290. .frame_vimax(frame_vimax),
     
291. .hd_clk_en(hd_clk_en),
     
292. .hi_fast(hi_fast),
     
293. .hi_slow(hi_slow),
     
294. .huffd_datavalid(huffd_datavalid),
     
295. .huffd_eob(huffd_eob),
     
296. .ns(ns),
     
297. .ri(ri),
     
298. .rst(rst),
     
299. .sen(sen),
     
300. .vi_fast(vi_fast),
     
301. .vi_slow(vi_slow),
     
302. .x(x),
     
303. .y(y),
     
304. .eos(eos_internal),
     
305. .hmcu(hmcu),
     
306. .huffd_res(huffd_res),
     
307. .mcu_csj(mcu_csj),
     
308. .vmcu(vmcu)
     
309. );
     
310. 
     
311. mux_1 lumchrmux (
     
312. .a(ht_cbus[2]),
     
313. .b(taj),
     
314. .s(ecs),
     
315. .y(huffd_lum_cr)
     
316. );
     
317. 
     
318. registerfile u_registerfile (
     
319. .clk(clk),
     
320. .din(streamdin),
     
321. .mcu_csj(mcu_csj),
     
322. .rst(rst),
     
323. .sof0_rf_addr(sof0_cbus[6:4]),
     
324. .sof0_rf_ci_w(sof0_cbus[3:2]),
     
325. .sof0_rf_clr(sof0_cbus[0]),
     
326. .sof0_rf_wen(sof0_cbus[1]),
     
327. .sos_rf_clr(sos_cbus[0]),
     
328. .sos_rf_csj(sos_cbus[3:2]),
     
329. .sos_rf_waddr(sos_cbus[4]),
     
330. .sos_rf_wen(sos_cbus[1]),
     
331. .ci_out(),
     
332. .hi_fast(hi_fast),
     
333. .hi_slow(hi_slow),
     
334. .nf(nf),
     
335. .ns(ns),
     
336. .p(),
     
337. .taj(taj),
     
338. .tdj(),
     
339. .tqi(tqi),
     
340. .vi_fast(vi_fast),
     
341. .vi_slow(vi_slow),
     
342. .x(x),
     
343. .y(y)
     
344. );
     
345. 
     
346. // Implicit buffered output assignments
     
347. assign eos = eos_internal;
     
348. 
     
349. endmodule
     
350. 
     

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Hi,
I would like to decrypt a protected verilog fileas your example, andyredcom@foxmail.com

how to decryp

how to decryption

I am learning about Huffman coding,could you please send me the Huffman coding program?my mail is 1991025456@qq.com,thanks a lot！