求 DesignWare DDR2/3-Lite Memory Controller IP
时间：03-15
整理：3721RD
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Does anyone provide DesignWare DDR2/3-Lite Memory Controller IP?
The Synopsys DesignWare® DDR2/3-Lite SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite physical layer (PHY) in a DDR3 or DDR2 memory subsystem. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data trAIning.
http://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr2-lite_mem
The Synopsys DesignWare® DDR2/3-Lite SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite physical layer (PHY) in a DDR3 or DDR2 memory subsystem. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data trAIning.
http://www.synopsys.com/dw/ipdir.php?ds=dwc_ddr2-lite_mem
这是讲工艺么?
No, it's DRAM controller.
Thanks..for the Info.
Thanks..
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Could you send the lice$en$e to me?
这个是要花很多咪咪的。
过年来赚钱！
eetop good
能发我一份么。
有IP Library可分享嗎?
这个能找到吗?