debussy nWave某些信号不显示
时间:03-15
整理:3721RD
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在nWave中不能显示Vhdl 使用generate for语法生成的代码信号,使用generate for语法有什么注意事项吗?
以下是一个我的例子
SRAM_Y:for i in 0 to 5 generate
SRAM_Y_i: entity work.blk_ram20x960
port map (
clka=> CLK_L,
ena=> w_scalery_mem_write_cs(i), --: IN STD_LOGIC;
wea=> w_scalery_mem_write_en, --: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra=> w_scalery_mem_write_addr(9 downto 0), --: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina=> w_scalery_mem_write_data, --: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb=> CLK_L, --: IN STD_LOGIC;
enb=> w_scalery_mem_read_en, --w_read_cs; --: IN STD_LOGIC;
addrb=> w_scalery_mem_read_addr(9 downto 0), --w_read_addr, --: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb=> w_memy_read_data((i+1)*2*BIT_WIDTH-1 downto i*2*BIT_WIDTH)--: OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end generate;
在nWave中不能显示clka,ena等信号名,能够显示CLK_L,w_scalery_mem_write_cs等信号。
以下是一个我的例子
SRAM_Y:for i in 0 to 5 generate
SRAM_Y_i: entity work.blk_ram20x960
port map (
clka=> CLK_L,
ena=> w_scalery_mem_write_cs(i), --: IN STD_LOGIC;
wea=> w_scalery_mem_write_en, --: IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra=> w_scalery_mem_write_addr(9 downto 0), --: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina=> w_scalery_mem_write_data, --: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb=> CLK_L, --: IN STD_LOGIC;
enb=> w_scalery_mem_read_en, --w_read_cs; --: IN STD_LOGIC;
addrb=> w_scalery_mem_read_addr(9 downto 0), --w_read_addr, --: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb=> w_memy_read_data((i+1)*2*BIT_WIDTH-1 downto i*2*BIT_WIDTH)--: OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
end generate;
在nWave中不能显示clka,ena等信号名,能够显示CLK_L,w_scalery_mem_write_cs等信号。
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