关于physical compiler
没人知道?
没用过icc
独立包........
ICC replace Physical compiler two years ago
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介绍
简介:
软件名称：Design Compiler
版本号： 200406SP2_2
软件语言： 英文
运行环境： Linux Redhat7.2 8.0,9.0/Redhat ES3
软件大小： 682 MB
软件分类： EDA/工具
主要内容如下：
Product List
ACE, BSD Compiler ,Behavioral Compiler ,CoCentric SystemC Compiler ,
DFT Compiler ,Design Compiler, Design Vision, DesignWare Developer ,
DesignWare Foundation ,External Interfaces, FloorPlan Manager, HDL Compiler ,
Library Compiler ,Module Compiler ,Physical Compiler ,Power Compiler,
Synthesis ,
DC Expert
DC Expert™ is the synthesis tool used on nearly every design in the electronics industry. It has been proven through tens of thousands of successful tape-outs and is supported by virtually all silicon and library vendors. DC Expert optimizes digital designs to provide the smallest, fastest logical representation of a given function. Synopsys continues to invest in DC Expert making it the complete synthesis solution addressing all design goals such as timing, test, power, and datapath and providing the fastest path to results for logical designers.
Key benefits:
1 Optimizes millions of logic elements
2 Allows users to control the optimization engine
3 Allows users to manage either flat or hierarchical designs, proceeding top-down or bottom-up
DC Ultra
DC Ultra™ is the best-in-class, production-proven register transfer level (RTL) synthesis solution. It enables users to meet today’s design challenges including increasing clock frequency and smaller die size mandates along with shorter design cycle time. A recent customer survey showed that
average designs in today’s environment are anything but average. They are complex and have stringent requirements. Today’s designs contain a high percentage of datapath while
operating at frequencies above 250 MHz. DC Ultra adds a comprehensive set of datapath and timing optimization techniques to the industry proven complete synthesis solution from Synopsys. It is the ideal choice for today’s designs.
Key benefits:
1 Delivers best quality of results (QoR) in terms of area and timing for designs with or without datapath
2 Removes timing bottlenecks by creating fast critical paths
3 Helps achieve timing closure faster by providing a tighter link with place and route environments for designs requiring two to four timing closure iterations for specific areas of designs
4 Offers faster runtimes and higher capacity with Automated Chip Synthesis
5 Enables higher efficiency with integrated static timing analysis, test synthesis, and power synthesis
Module Compiler
Increasing complexity and decreasing time to market for graphics, video, DSP, and communications applications are magnifying the need to create special-purpose, highly tuned datapath modules. To meet the requirements of these performance-driven products, designers need a tool that allows them to reuse known datapath structures. Synopsys Module Compiler™ is a module compilation tool that enables designers to reuse their datapath structures to obtain the best implementation for their designs.
Key benefits:
1 Accelerates time to quality
2 Provides improved quality of results
3 Increases designer productivity
4 Provides quickest path to performance while maintaining technology independence and a high level of reuse
Physical Compiler
Physical Compiler®, the cornerstone of Synopsys’ physical synthesis solution and a key component of Synopsys’ Galaxy™ Design Platform, enables register-transfer level (RTL) designers to deliver the highest-performance circuits in the shortest time. By unifying synthesis and placement, Physical
Compiler offers designers predictable timing closure from RTL to placed-gates for their most complex designs. Proven interfaces to third-party routers allow it to easily plug into an existing design flow.
Built upon the industry-standard Design Compiler®, Physical Compiler works seamlessly with Synopsys’ floor planning, power, datapath, test, routing, and DesignWare® solutions. Physical Compiler has been widely adopted by the design community with over a thousand tapeouts attributed to it. Physical Compiler enables customers to meet their time to market requirements with significant performance and productivity gains. All major ASIC vendors have design kit support for Physical Compiler and are using placement handoff to quickly close timing on their most complex designs.
Key benefits:
1 Delivers best QoR in terms of timing, power, area, and routability
2 Easy to adopt–Similar TCL environment to that of Design Compiler®, with a rich super set of powerful
commands and easy-to use graphical user interface (GUI) to get up and running quickly, and get the job done
3 Ensures consistent timing, constraints and library throughout Synopsys tools
4 Leverages customer investment
5 Plug-and-play solution for third-party place-and-route flows—industry standard format interfaces ensure smooth adoption
6 Comprehensive ASIC vendor support—users have the flexibility to choose between ASIC vendors and still maintain control over their design QoR and CAD tools
7 Fast and accurate implementation feasibility analysis –built-in register transfer level (RTL) Performance Prototyping (RPP) and quick placement mode help save time when exploring the effect of physical implementation on RTL architectural options during early stages of the design
8 Very fast runtimes for large (1M to 2M instances) flat chip designs with distributed physical synthesis (DPS)
9 Direct Milkyway™ integration and RC model support enables a consistent and convergent flow with Astro for faster time to results
10 Global router integration for better timing predictability on congested designs (required PC Expert option)
11 Fast multi-Vth flow with Power Compiler for leakage optimization
12 Opteron 32/64 bit availability starting with v2003.12 for faster runtimes
DFT Compiler
DFT Compiler™ is the next generation 1-pass test synthesis solution, which makes design-for-test (DFT) implementation transparent in the Synopsys’ physical synthesis flow, without interfering with the designers’ need to meet functional, timing, power and physical requirements. DFT Compiler includes capabilities available in 1-Pass test synthesis along with RTL Test DRC and AutoFix, and adds significant new capabilities including: Hierarchical Scan Synthesis; Unified Test Design Rule Checking from RTL to gates; Rapid Scan Synthesis; Scan-based test data volume reduction, and integration with
Physical Compiler® to support scan ordering based on physical placement information. The integration of test within the Physical Compiler environment ensures predictable timing closure and achieves physically optimized scan designs, reducing congestion and improving routability.
Key benefits:
1 Shortens the overall design cycle by transparent DFT implementation within the synthesis flow
2 Increases productivity by accounting for testability early in the design cycle at the RTL
3 Removes unpredictability from the back end of the design process
4 Drastically reduces design iterations and schedule risks by achieving predictable timing closure
Power Compiler
Synopsys’ Power Compiler™ provides dynamic and leakage power optimization at RTL and gate-level within Synopsys’ synthesis and physical design flow. At the RTL, during the design elaboration phase, Power Compiler performs automatic clock gating to reduce the power consumption. At the gate level, driven by the designer constraints, it performs simultaneous optimization for timing, power and
area. Offered within the Galaxy™ Design Platform, Power Compiler shares the same GUI, commands, constraints and libraries with Design Compiler® and Physical Compiler®.
Key benefits:
1 Dynamic and leakage power optimization at RTL and gate-level within Synopsys’ synthesis and physical design flow
2 Tapeout-proven by leading semiconductor companies
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ｉｎｓｔａｌｌｅｒ是安装的工具，必须运行ｉｎｓｔａｌｌｅｒ才能安装该软件。
介绍
简介:
软件名称：Design Compiler
版本号： 200406SP2_2
软件语言： 英文
运行环境： Linux Redhat7.2 8.0,9.0/Redhat ES3
软件大小： 682 MB
软件分类： EDA/工具
主要内容如下：
Product List
ACE, BSD Compiler ,Behavioral Compiler ,CoCentric SystemC Compiler ,
DFT Compiler ,Design Compiler, Design Vision, DesignWare Developer ,
DesignWare Foundation ,External Interfaces, FloorPlan Manager, HDL Compiler ,
Library Compiler ,Module Compiler ,Physical Compiler ,Power Compiler,
Synthesis ,