Which is best for TLM simulation？ 1-Questa 2-IUS 3-VCS

As you know, these 3 tools have been used mostly for functional verification especially for designs written in verilog, SystemVerilog and Vhdl since long time ago. But with appearance of TLM-2 standard by systemc.org and now accelera.org for bus-based soc designs (and of course in the future, network on chip) some tools emerged for satisfying the users' need in designing complex bus-based SOC comprising IPs, memories, cpu models, and other peripherals. Among them, 3 giants EDA venders' tools can be named. 1- Mentor Vista, 2- Cadence System Development Suite and 3- Synopsys Platform architect.
But still they perform lots of their simulations with legacy tools like Questa, IUS and VCS. I want to know has anyone tried to use these tools for the purpose of TLM simulation?

接触过questa和vcs，questa完全就是modelsim升级版，界面都完全一样，vcs正在探索中，还不太了解。

学习一下

使用过vcs 目前正在用questasim，这两个工具都差不多