veriloge语言编写自动售货机在modelsim上仿真，求指导

（1） 可投5角和一元两种硬币；

（2） 饮料单价为2.5元；

（3） 系统能够根据用户输入的硬币，判断钱币是否足够，当所投硬币达到或者超过购买者所选面值时，则根据顾客的要求自动售货，并找回剩余的硬币，然后回到初始状态，当所投硬币面值不够时，则给出提示，并通过一个复位键退回所投硬币。然后回到初始状态。

给多少钱呢

很简单的啊，看看状态机怎么写的不就会了

状态机是正解

一点也没接触过这个东西，不过终于钻研出来程序了，但是测试文件老是不对，麻烦给指导一下
module shouhuoji(one_dollar,half_dollar,collect,half_out,can_out,reset,clk);
parameter idle=0,one=2,half=1,two=3,three=4;
//idle,one,half,two,three?
input one_dollar,half_dollar,reset,clk;
output collect,half_out,can_out;
reg collect,half_out,can_out;
reg[2:0] D;
always @(posedge clk)
begin if(reset)
begin can_out=0;collect=0;half_out=0;D=idle;end
case(D)
idle:if(half_dollar)D=half;
else if(one_dollar)D=one;
half:if(half_dollar)D=one;
else if(one_dollar)D=two;
one:if(half_dollar)D=two;
else if(one_dollar)D=three;
two:if(half_dollar)D=three;
else if(one_dollar)
begincan_out=1;//?
collect=1; D=idle;
end
three: if(half_dollar)
begincan_out=1;//?
collect=1; D=idle;
end
else if(one_dollar)
begin can_out=1;//?
collect=1;half_out=1;D=idle;
end
endcase
end
endmodule
测试：
`timescale 1s/1s
module task_tb;
reg one_dollar,half_dollar,reset,clk;
wire collect,half_out,can_out;
parameter Time=2;
task t1(one_dollar,half_dollar,collect,half_out,can_out,reset,clk);
always#(Time/2) clk=~clk;
initial
begin
clk=1;reset=0;one_dollar=0;half_dollar=0;
#Timereset=1;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timehalf_dollar=1;
#Timehalf_dollar=0;
//
#Timereset=1;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Time$finish;
end
initial $monitor($time,,,"clk=%d reset=%d half_dollar=%d one_dollar=%d can_out=%d half_out=%d collect=%d ",clk,reset,half_dollar,one_dollar,can_out,half_out,collect);
endmodule

终于钻研出来程序了，但是测试文件老是不对，麻烦给指导一下
module shouhuoji(one_dollar,half_dollar,collect,half_out,can_out,reset,clk);
parameter idle=0,one=2,half=1,two=3,three=4;
//idle,one,half,two,three?
input one_dollar,half_dollar,reset,clk;
output collect,half_out,can_out;
reg collect,half_out,can_out;
reg[2:0] D;
always @(posedge clk)
begin if(reset)
begin can_out=0;collect=0;half_out=0;D=idle;end
case(D)
idle:if(half_dollar)D=half;
else if(one_dollar)D=one;
half:if(half_dollar)D=one;
else if(one_dollar)D=two;
one:if(half_dollar)D=two;
else if(one_dollar)D=three;
two:if(half_dollar)D=three;
else if(one_dollar)
begincan_out=1;//?
collect=1; D=idle;
end
three: if(half_dollar)
begincan_out=1;//?
collect=1; D=idle;
end
else if(one_dollar)
begin can_out=1;//?
collect=1;half_out=1;D=idle;
end
endcase
end
endmodule
测试：
`timescale 1s/1s
module task_tb;
reg one_dollar,half_dollar,reset,clk;
wire collect,half_out,can_out;
parameter Time=2;
task t1(one_dollar,half_dollar,collect,half_out,can_out,reset,clk);
always#(Time/2) clk=~clk;
initial
begin
clk=1;reset=0;one_dollar=0;half_dollar=0;
#Timereset=1;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timehalf_dollar=1;
#Timehalf_dollar=0;
//
#Timereset=1;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Timeone_dollar=1;
#Timeone_dollar=0;
#Time$finish;
end
initial $monitor($time,,,"clk=%d reset=%d half_dollar=%d one_dollar=%d can_out=%d half_out=%d collect=%d ",clk,reset,half_dollar,one_dollar,can_out,half_out,collect);
endmodule