我的测试模块无法调用！

我正在学习使用modelsim，敲了个例子，三个模块都编译成功了，就是测试模块无法调用（始终显示如下的提示），还请高手指教！
会不会是例子代码本身的问题?
# Loading work.campare
# Loading work.blocking
# Loading work.non_blocking
# ** Warning: (vsim-3015) E:/program fAIls/ModelSim/my fails/excise/compare.v(23): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'clk'.
#Region: /campare/U2
# ** Error: (vsim-3053) E:/program fails/ModelSim/my fails/excise/compare.v(23): Illegal output or inout port connection (port 'c2').
#Region: /campare/U2
# ** Warning: (vsim-3015) E:/program fails/ModelSim/my fails/excise/compare.v(23): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'c2'.
#Region: /campare/U2
# Error loading design
module blocking(a,b1,c1,clk);
input[3:0] a;
input clk;
output [3:0] b1,c1;
reg [3:0] b1,c1;
always @(posedge clk)
begin
b1=a;
c1=b1;
$display("blocking: a=%d b1=%d c1=%d" ,a,b1,c1);
end
endmodule
module non_blocking(clk,a,b2,c2);
output [3:0] b2,c2;
input [3:0] a;
input clk;
reg [3:0] b2,c2;
always @(posedge clk)
begin
b2<=a;
c2<=b2;
$display("non_blocking: a=%d b2=%d c2=%d" ,a,b2,c2);
end
endmodule
wire[3:0] b1,c1,b2,c2;
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
a=4'h3;
$display ("_______________________");
#100 a=4'h7;
$display ("_______________________");
#100 a=4'hf;
$display ("_______________________");
#100 a=4'ha;
$display ("_______________________");
#100 a=4'h2;
$display ("_______________________");
#100 $display ("_______________________");
end
blocking U1(a,b1,c1,clk);
non_blocking U2(a,b2,c2,clk);
endmodule

怎么没有大侠帮帮 ?

看看compare文件中U2的端口次序，应该和module描述中的一致。

谢了，果然是这个问题！