什么是反谐振电路呢？antiresonant circuit
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The condition for which the impedance of a given electric, acoustic, or dynamic system is very high, approaching infinity. In an electric circuit consisting of a capacitor and a coil in parallel, antiresonance occurs when the alternating-current line voltage and the resultant current are in phase.[1]
Under these conditions the line current is very small because of the high electrical impedance of the parallel circuit at antiresonance. The branch currents are almost equal in magnitude and opposite in phase.[2]
The principal of antiresonance is used in wave traps, which are sometimes inserted in series with antennas of radio receivers to block the flow of alternating current at the frequency of an interfering station, while allowing other frequencies to pass.[3] [4]
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Anti-resonance 1
并联谐振 2
图 7
Anti-resonance
The condition for which the impedance of a given electric, acoustic, or dynamic system is very high, approaching infinity. In an electric circuit consisting of a capacitor and a coil in parallel, antiresonance occurs when the alternating-current line voltage and the resultant current are in phase.[1]
Under these conditions the line current is very small because of the high electrical impedance of the parallel circuit at antiresonance. The branch currents are almost equal in magnitude and opposite in phase.[2]
The principal of antiresonance is used in wave traps, which are sometimes inserted in series with antennas of radio receivers to block the flow of alternating current at the frequency of an interfering station, while allowing other frequencies to pass.[3] [4]
Anti-resonance
When capacitors with different capacitance exist on the PCB, high impedance can occur in between the self-resonant frequencies. This phenomenon is called anti-resonance. Anti-resonance not only occurs between capacitors but also amongst power planes, chip and package. If anti-resonance frequency overlaps with fundamental clock and its harmonics it significantly affects power integrity. In order to improve power integrity, it is crucial to reduce anti-resonance.
Reduce plane distance
Reducing distance between power and ground planes will increase capacitance and reduce parasitic inductance (L). Therefore, you can eliminate power bus noise by optimizing the distance between power and ground planes. Typically, when determining stackup, signal impedance and routing are prioritized. However, dielectric thickness is crucial for power integrity as well so it needs to be taken into consideration.
Chip/PKG/PCB total analysis
Taking into account effects of capacitors, chip and package is critical for performing accurate power integrity analysis.
This figure shows that the package inductance (L) increases with less number of power pins, relatively increasing effects of the package.
In order to maximize power integrity improvement at PCB level, you need to optimize the number of power pins to reduce parasitic inductance (L) elements of the package.
并联谐振
并联谐振
英文名称：
parallel resonance
电流谐振
定义：
在发生谐振时一端口网络内相并联的两个子网络的无功电流分量相互抵消。
所属学科：
电力（一级学科） ；通论（二级学科）
本内容由全国科学技术名词审定委员会审定公布
概述
在电感和电容并联的电路中，当电容的大小恰恰使电路中的电压与电流同相位，即电源电能全部为电阻消耗，成为电阻电路时，叫作并联谐振。
并联谐振是一种完全的补偿，电源无需提供无功功率，只提供电阻所需要的有功功率。谐振时，电路的总电流最小，而支路的电流往往大于电路的总电流，因此，并联谐振也称为电流谐振。
发生并联谐振时，在电感和电容元件中流过很大的电流，因此会造成电路的熔断器熔断或烧毁电气设备的事故；但在无线电工程中往往用来选择信号和消除干扰。
lc并联谐振电路之电源可分为电压源及电流源两种，分别讨论如下：
1. 电源为电压源之并联谐振电路：
(1) 并联谐振电路之条件如图(1)所示：
图1
(2)当 QL = QC 也就是 XL = XC 或 BL = BC 时，为R-L-C 并联电路产生谐振之条件。
(2) 并联谐振电路之特性：
电路阻抗最大且为纯电阻。即
电路电流为最小。即
电路功率因数为1。即
电路平均功率固定。即
电路总虚功率为零。即QL=QC⇒QT=QL-QC=0
※并联谐振又称为反谐振，因其阻抗及电流之大小与串联谐振时相反。
(3) 并联谐振电路的频率：
公式：
R-L-C 并联电路欲产生谐振时，可调整电源频率f 、电感器L 或电容器
C 使其达到谐振频率f r ，而与电阻R 完全无关(与串联电路完全相同)。
(4) 并联谐振电路之品质因数：
定义：电感器或电容器在谐振时产生的电抗功率与电阻器消耗的平均
功率之比，称为谐振时之质量因子。
公式：
品质因子Q值愈大表示电路对谐振时响应愈佳。
(5) 并联谐振电路导纳与频率之关系如图(2)所示：
电导G 与频率无关，系一常数，故为一横线。
电感纳 ，与频率成反比，故为一曲线。
电容纳 BC= 2πfC ，与频率成正比，故为一斜线。
导纳 Y=G+ j（BC- BL）
当 f = fr 时， BC＝ BL ， Y = G ( Z= R 为最大值)，电路为电阻性。
当f ＞ fr 时， BC ＞ BL ，电路为电容性。
当f ＜ fr 时， BL ＞ BC ，电路为电感性。
当f = 0 或f = ∞ 时，Y = ∞ ， Z = 0 ，电路为短路。
若将电源频率f 由小增大，电路导纳Y 的变化为先减后增，阻抗Z 的
变化则为先增后减。
图(2) 图(3)
(6) 并联谐振电路之选择性如图(3)所示：
当f = fr 时， ，此频率称为谐振频率。
当 f = f1 或 f2 时， ，此频率称为旁带频率或截止频率。
并联谐振电路之选择性：电路电流最小值变动至 倍电流最小值时，
其所对应的两旁带频率间之范围，即为该电路之选择性，通常称为频
带宽度或波宽，以BW 表示。
公式：
f 2> fr 称为上限截止频率，f 1< fr 称为下限截止频率。
公式：
若将电源频率f 由小增大，则电路电流I 的变化为先减后增，而质量因
数Q值愈大，其曲线越尖锐，即频带宽度越窄，响应越好，选择性越
佳。
2. 电源为电流源之并联谐振电路如图(4)所示：
(1) 并联谐振电路之特性：
输出电压为最大。即 Vo =I Z=IR 平均输出功率为最大。即
(2) 并联谐振电路之品质因数：
公式：
图(4) 图(5)
(3) 并联谐振电路之选择性如图(5)所示：
当 f = fr 时，Vo =Vmax ，此频率称为谐振频率。
当 f = f1 或 f 2时， 此频率称为旁带频率、截止频率或半功率频率。
当f = f1 或 f2 时，其电路功率为最大功率之半，故截止频率又称为半功率频率。
公式：
其余并联谐振之各项性质、公式均与电源为电压源并联谐振时相同。
图