请各位大神看看代码，产生两路脉冲的verilog程序

module single_pulse(pulse_out1,pulse_out2,width1,delay,clk,rst,start);
  output pulse_out1;
output pulse_out2;
  input clk,rst,start;
  input [7:0] width1;
  input [7:0] width2;
  input [15:0] delay;
  reg load;
  reg pulse_out1;
  reg [7:0] count1;
reg [7:0] count2;
  reg [15:0] count3;
  reg [3:0] cnt;
always@(posedge clk or negedge rst)
begin
  if(~rst)
  begin
    cnt<=4'd10;
    load<=1'd0;
  end
else
  begin
  cnt<=cnt-1'd1;
  if(cnt==1'd0)
          begin
                cnt<=3'd5;
                load<=1'd1;
     end
  end
end
always@(posedge clk or negedge rst)
  begin
  if(~rst)
  begin
        count1 <= width1;
        count2 <= width2;
        count3 <= delay;
        pulse_out1<= 1'd0;
        pulse_out2<= 1'd1;
  end
  else  if(load == 1'd1)
  begin
  if(start == 1'd1 )
  begin
    if(count1)
         begin
    count1 <= count1-8'd1;
    pulse_out1 <= 1'd1;
         end
   else
   begin
   pulse_out1 <= 1'd0;
   end
       
        if(count3)
        begin
        count1 <= count1-8'd1;
        pulse_out2 <= 1'd1;
        end
        else
        begin
        if(count2)
        begin
        count2<=count2-8'd1;
        pulse_out2<=1'd0;
        end
        else
        begin
        pulse_out2<=1'd1;
        end
  end
end
end
endmodule
这段编译结果Error (10170): Verilog HDL syntax error at single_pulse.v(75) near text "endmodule";  expecting "end"，不知道怎么改了，我是为了产生两个可调脉冲，相隔一定时间的。

还有就是这第二个pulse_out2输出该如何实现延时可调呢

语法问题，不是end用多了就是用少了

楼上正解。没有缩进，错误都不好找

小编，你少写了一个end