加入Chipscope的CDC文件后，MAP报错，求指导！
时间：10-02
整理：3721RD
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最近在研究Ettus Reseach的B210软件无线电开发板，想要在原版FPGA工程里做自己的一些设计，所以需要将一些信号拉出来观察。现在情况是，没有加入CDC之前，Map是没有问题的，打算拉出几个信号来看，加入CDC文件，始终在Map处报错。ps：芯片是Spartan-6 xc6slx150-3fgg484。
报错如下：
ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Map详细报告：
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 32,715 out of 184,304 17%
Number used as Flip Flops: 32,640
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 74
Number of Slice LUTs: 31,416 out of 92,152 34%
Number used as logic: 24,883 out of 92,152 27%
Number using O6 output only: 18,758
Number using O5 output only: 1,208
Number using O5 and O6: 4,917
Number used as ROM: 0
Number used as Memory: 5,630 out of 21,680 25%
Number used as Dual Port RAM: 992
Number using O6 output only: 88
Number using O5 output only: 14
Number using O5 and O6: 890
Number used as Single Port RAM: 0
Number used as Shift Register: 4,638
Number using O6 output only: 3,207
Number using O5 output only: 1
Number using O5 and O6: 1,430
Number used exclusively as route-thrus: 903
Number with same-slice register load: 802
Number with same-slice carry load: 101
Number with other load: 0
Slice Logic Distribution:
Number of MUXCYs used: 14,432 out of 46,076 31%
Number of LUT Flip Flop pairs used: 37,874
Number with an unused Flip Flop: 8,628 out of 37,874 22%
Number with an unused LUT: 6,458 out of 37,874 17%
Number of fully used LUT-FF pairs: 22,788 out of 37,874 60%
Number of unique control sets: 835
Number of slice register sites lost
to control set restrictions: 2,585 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 178 out of 338 52%
Number of LOCed IOBs: 178 out of 178 100%
IOB Flip Flops: 184
Specific Feature Utilization:
Number of RAMB16BWERs: 181 out of 268 67%
Number of RAMB8BWERs: 11 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 5 out of 32 15%
Number used as BUFIO2s: 4
Number used as BUFIO2_2CLKs: 1
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 4
Number used as BUFGMUX: 1
Number of DCM/DCM_CLKGENs: 1 out of 12 8%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 57 out of 586 9%
Number used as ILOGIC2s: 57
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 10 out of 586 1%
Number used as IODELAY2s: 10
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 85 out of 586 14%
Number used as OLOGIC2s: 85
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 152 out of 180 84%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Number of RPM macros: 9
Design Summary
--------------
Number of errors : 3
Number of warnings : 2
ERROR:Place:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
FF 135 (0.5)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig000006af
1. FF b200_core/radio_0/new_rx_framer/datafifo/fifo_bram/o_tdata
2. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000069b
3. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig000006fd
4.
b200_core/radio_0/convert_xxxx_to_16sc/convert_32f_to_16sc/float_to_iq_imag1/
n0057 _FRB (size: 2)
FF
b200_core/radio_0/convert_xxxx_to_16sc/convert_32f_to_16sc/float_to_iq_imag1/
n0057 _FRB
FF
b200_core/radio_0/convert_xxxx_to_16sc/convert_32f_to_16sc/float_to_iq_imag1/
n0057 _FRB
5. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig0000031f
6. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig00000338
7. b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig0000074b (size:
2)
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk000004cf
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk000004ce
8. b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig00000764 (size:
2)
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk00000498
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk00000497
9. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig00000699 (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004dd
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004dc
10. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig00000709 (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk00000362
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk00000361
11. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig000006ab
12. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000074b (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004cf
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004ce
13. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000068a
14. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000067c (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk0000011f
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk0000011e
15. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig0000038f
16. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig00000340
17.
b200_core/radio_0/tx_fifo/fifo_4k_2clk/U0/xst_fifo_generator/gconvfifo.rf/grf
.rf/rstblk/rd_rst_asreg_d2 (size: 2)
FF
b200_core/radio_0/tx_fifo/fifo_4k_2clk/U0/xst_fifo_generator/gconvfifo.rf/grf
.rf/rstblk/rd_rst_asreg_d2
FF
b200_core/radio_0/tx_fifo/fifo_4k_2clk/U0/xst_fifo_generator/gconvfifo.rf/grf
.rf/rstblk/rd_rst_asreg_d1
。
94. FF b200_core/radio_1/ddc_chain/new_hb.hbdec1/blk00000003/sig00000325
95. FF
slave_fifo32/gpif2_to_fifo64_ctrl/cross_clock_fifo/fifo_short_2clk/U0/xst_fif
o_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_
stg_inst/D
96. FF
b200_core/radio_1/resp_fifo/fifo_short_2clk/U0/xst_fifo_generator/gconvfifo.r
f/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg
97. FF
b200_core/radio_1/resp_fifo/fifo_short_2clk/U0/xst_fifo_generator/gconvfifo.r
f/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D
98. FF b200_core/radio_1/duc_chain/new_hb.hb1_q0/data_in_pipe_1723
99. FF slave_fifo32/gpif2_to_fifo64_ctrl/cross_clock_fifo/full
。
报错如下：
ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Map详细报告：
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 32,715 out of 184,304 17%
Number used as Flip Flops: 32,640
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 74
Number of Slice LUTs: 31,416 out of 92,152 34%
Number used as logic: 24,883 out of 92,152 27%
Number using O6 output only: 18,758
Number using O5 output only: 1,208
Number using O5 and O6: 4,917
Number used as ROM: 0
Number used as Memory: 5,630 out of 21,680 25%
Number used as Dual Port RAM: 992
Number using O6 output only: 88
Number using O5 output only: 14
Number using O5 and O6: 890
Number used as Single Port RAM: 0
Number used as Shift Register: 4,638
Number using O6 output only: 3,207
Number using O5 output only: 1
Number using O5 and O6: 1,430
Number used exclusively as route-thrus: 903
Number with same-slice register load: 802
Number with same-slice carry load: 101
Number with other load: 0
Slice Logic Distribution:
Number of MUXCYs used: 14,432 out of 46,076 31%
Number of LUT Flip Flop pairs used: 37,874
Number with an unused Flip Flop: 8,628 out of 37,874 22%
Number with an unused LUT: 6,458 out of 37,874 17%
Number of fully used LUT-FF pairs: 22,788 out of 37,874 60%
Number of unique control sets: 835
Number of slice register sites lost
to control set restrictions: 2,585 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 178 out of 338 52%
Number of LOCed IOBs: 178 out of 178 100%
IOB Flip Flops: 184
Specific Feature Utilization:
Number of RAMB16BWERs: 181 out of 268 67%
Number of RAMB8BWERs: 11 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 5 out of 32 15%
Number used as BUFIO2s: 4
Number used as BUFIO2_2CLKs: 1
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 4
Number used as BUFGMUX: 1
Number of DCM/DCM_CLKGENs: 1 out of 12 8%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 57 out of 586 9%
Number used as ILOGIC2s: 57
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 10 out of 586 1%
Number used as IODELAY2s: 10
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 85 out of 586 14%
Number used as OLOGIC2s: 85
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 152 out of 180 84%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Number of RPM macros: 9
Design Summary
--------------
Number of errors : 3
Number of warnings : 2
ERROR:Place:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
FF 135 (0.5)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig000006af
1. FF b200_core/radio_0/new_rx_framer/datafifo/fifo_bram/o_tdata
2. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000069b
3. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig000006fd
4.
b200_core/radio_0/convert_xxxx_to_16sc/convert_32f_to_16sc/float_to_iq_imag1/
n0057 _FRB (size: 2)
FF
b200_core/radio_0/convert_xxxx_to_16sc/convert_32f_to_16sc/float_to_iq_imag1/
n0057 _FRB
FF
b200_core/radio_0/convert_xxxx_to_16sc/convert_32f_to_16sc/float_to_iq_imag1/
n0057 _FRB
5. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig0000031f
6. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig00000338
7. b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig0000074b (size:
2)
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk000004cf
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk000004ce
8. b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig00000764 (size:
2)
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk00000498
FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/blk00000497
9. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig00000699 (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004dd
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004dc
10. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig00000709 (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk00000362
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk00000361
11. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig000006ab
12. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000074b (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004cf
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk000004ce
13. FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000068a
14. b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/sig0000067c (size:
2)
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk0000011f
FF b200_core/radio_1/ddc_chain/new_hb.hbdec2/blk00000003/blk0000011e
15. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig0000038f
16. FF b200_core/radio_0/ddc_chain/new_hb.hbdec2/blk00000003/sig00000340
17.
b200_core/radio_0/tx_fifo/fifo_4k_2clk/U0/xst_fifo_generator/gconvfifo.rf/grf
.rf/rstblk/rd_rst_asreg_d2 (size: 2)
FF
b200_core/radio_0/tx_fifo/fifo_4k_2clk/U0/xst_fifo_generator/gconvfifo.rf/grf
.rf/rstblk/rd_rst_asreg_d2
FF
b200_core/radio_0/tx_fifo/fifo_4k_2clk/U0/xst_fifo_generator/gconvfifo.rf/grf
.rf/rstblk/rd_rst_asreg_d1
。
94. FF b200_core/radio_1/ddc_chain/new_hb.hbdec1/blk00000003/sig00000325
95. FF
slave_fifo32/gpif2_to_fifo64_ctrl/cross_clock_fifo/fifo_short_2clk/U0/xst_fif
o_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_
stg_inst/D
96. FF
b200_core/radio_1/resp_fifo/fifo_short_2clk/U0/xst_fifo_generator/gconvfifo.r
f/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg
97. FF
b200_core/radio_1/resp_fifo/fifo_short_2clk/U0/xst_fifo_generator/gconvfifo.r
f/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D
98. FF b200_core/radio_1/duc_chain/new_hb.hb1_q0/data_in_pipe_1723
99. FF slave_fifo32/gpif2_to_fifo64_ctrl/cross_clock_fifo/full
。
同求
后来改用了chipscope的IP核，发现根据拉出来的信号，有些信号MAP可以通过，有些则不行。报的错误与之前一样，说是有很多FF failed to place。
在XILINX官网上找到Place - How do I debug a "Place:543" error?
但是看不太懂。
https://www.xilinx.com/support/answers/35539.html
原工程里对上了SMARTGUIDE，去掉这个设置，再把工程里的xxx_guide.ncd文件删掉后，问题解决。