关于vivado的sim问题求解！
[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Administrator/Desktop/shuma/shumaxianshi/shumaxianshi.sim/sim_1/behav/xvlog.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
语言为verilog
这个问题怎么解决哇
哭死了要
是一个数码管的课设，显示花型
我劝你还是把代码贴出来，
好的
module top #(parameter WIDTH =32 )(seg7,scan,clk);//?
output [7:0]seg7;
input clk;
output [3:0]scan;
// reg clk;
reg clk1; //?
reg reset,reset1;
// reg button;
wire memread,memwrite;
wire [WIDTH-1:0] adr,writedata;
wire [WIDTH-1:0] memdata;
wire [WIDTH-1:0] rd3;
wire[3:0] scan ;
wire [7:0] seg7 ;
reg count1=0;
reg clk1=0;
//always@(negedge button)
//begin
//end
always @ (posedge clk)
begin
if(count1==1)
begin clk1 rd
RAM[3] >a);
6'b000011: result >>a);
6'b001000: result 0 ? 0:1);
end
6'b010001: result<=((b<<16)& 32'b11111111111111110000000000000000);//LUI
endcase
end
endmodule
//regfile
module regfile #(parameter WIDTH=32,REGBITS=5)
(input clk,
input reset,
input regwrite,
input [REGBITS-1:0] ra1,ra2,wa,
input [WIDTH-1:0] wd,
output [WIDTH-1:0] rd1,rd2,rd3);
reg [WIDTH-1:0] RAM2 [(1<<REGBITS)-1:0];
initial
begin
//$readmemh("regfile.dat",RAM);
RAM2[0] <=32'b00000000000000000000000000000000;
RAM2[1] <=32'b11111111111111111111111111111111;
RAM2[8] <=32'b00000000000000000000000000010000;//地址 %
RAM2[9] <=32'b00000000000000000000000000000000;//要找的数
RAM2[10]<=32'b00000000000000000000000000000000;//内存中取来的数
RAM2[15]<=32'b00000000000000000000000000000001;//常数1
RAM2[12]<=32'b00000000000000000000001000000000;
RAM2[11]<=32'b00000000000000000000000000010110;//末位+1的地址 %
RAM2[13]<=32'b00000000000000000000000000000000;//读入的数暂存
RAM2[14]<=32'b00000000000000000000000000011010;//%
RAM2[16]<=32'b00000000000000000000000000000000;//数码管输出寄存器
//RAM2[31]<=32'b00000000000000001010101111001101;//00000000000000000001001000110100;
end
always @(posedge clk)
if(regwrite)
RAM2[wa]<=wd;
assign rd1 =ra1 ? RAM2[ra1]:0;
assign rd2 =ra2 ? RAM2[ra2]:0;
assign rd3 =RAM2[16];
endmodule
//zerodetect ?0?beq?
module zerodetect #(parameter WIDTH=32)
(input [WIDTH-1:0] a,
output y);
assign y= (a==0);
endmodule
//flop ?
module flop #(parameter WIDTH =32)
(input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk)
q<=d;
endmodule
//flopen
module flopen #(parameter WIDTH =32)
(input clk,en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk)
if(en)
q<=d;
endmodule
//flopenr
module flopenr #(parameter WIDTH =32)
(input clk,reset,en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk)
if(reset)
q<=0;
else
if(en)
q<=d;
endmodule
//mux2
module mux2 #(parameter WIDTH =32)
(input [WIDTH-1:0] d0,d1,
input s,
output [WIDTH-1:0] y);
assign y= s ? d1:d0;
endmodule
//mux4
module mux4 #(parameter WIDTH =32)
(input [WIDTH-1:0] d0,d1,d2,d3,
input [1:0] s,
output reg [WIDTH-1:0] y);
always @(*)
case(s)
2'b00: y<= d0;
2'b01: y<= d1;
2'b10: y<= d2;
2'b11: y<= d3;
endcase
endmodule
以上为verilog源程序，上午调试的过程中发现只要把 reg clk1这一行注释掉就能够仿真，不过仿真结果不正确
编译错误了，你确定你这代码综合，实现可以通过?撇开其他模块，这个top模块你得多检查检查，感觉有点是tb文件（PS:以后贴代码别把无用的代码都贴出来）
我是小白，但是我也遇到过几次你的第一个错误，竟然都是程序里变量拼错了。仅供参考